| Patent application number | Description | Published |
|---|
| 20080205146 | Nonvolatile RAM - A nonvolatile RAM for reading and writing data in a random manner includes a memory area configured by a plurality of memory cells suited to a nonvolatile-mode write operation, in which the stored content thereof is not lost irrespective of a power-off event, and a volatile-mode write operation, in which the stored content thereof is lost in the power-off event. A register designates a first portion of the memory area adapted to the nonvolatile-mode write operation regarding fixed data such as program codes and a second portion of the memory area serving as a work area adapted to the volatile-mode write operation. A control circuit performs the nonvolatile-mode write operation on the first portion of the memory area while performing the volatile-mode write operation on the second portion of the memory area. | 08-28-2008 |
| 20080209117 | Nonvolatile RAM - A nonvolatile RAM allows a read/write operation to be performed in a random manner with respect to a memory area, which is divided into a plurality of memory arrays each including a plurality of memory cells. Upon detection of an initialization signal, initialization is performed on at least one memory array, which is selected in advance. In addition, a disconnection control signal occurs so as to disconnect an access by an external device during a prescribed period for performing the initialization. The nonvolatile RAM is capable of protecting data from being irregularly read, modified, and reloaded with respect to at least one memory array, which is selected in advance, even when the nonvolatile RAM is frequently accessed by a prescribed application. | 08-28-2008 |
| 20080232155 | MOLECULAR BATTERY MEMORY DEVICE AND DATA PROCESSING SYSTEM USING THE SAME - Each memory cell of a molecular battery memory device includes a combination of a molecular battery and a selection transistor, and a parasitic capacitance is present in the molecular battery. A PN junction is present in the selection transistor, and is inversely biased. Therefore, a junction leak current flows. Accordingly, a charge accumulated in the parasitic capacitance is gradually discharged by a junction leak of the selection transistor, and a final potential of a node decreases toward a substrate potential Vs of the transistor. However, a difference between a substrate potential Vs and a reference potential Vp (=Vs−Vp) is set substantially equal to an open-circuit voltage of the molecular battery. Because the potential of the node converges to the open-circuit voltage without exception from the viewpoint of a plate wiring, an S/N ratio at the data reading time can be increased. | 09-25-2008 |
| 20080253159 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; global sense amplifiers for amplifying the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line and for selectively coupling the signal to an external data line. | 10-16-2008 |
| 20080259707 | Semiconductor storage device - A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side of bit lines and switching a connecting state between the other row of sense amplifiers and the other side of bit lines; a control means which sets at least one row of sense amplifiers as a cache memory, and when performing refresh operation of the unit block where row of sense amplifiers to be used as cache memory holds data, controls switch means so that the row of sense amplifiers used as cache memory is disconnected from bit lines and only the row of sense amplifiers not used as said cache memory is used in refresh operation. | 10-23-2008 |
| 20080276049 | Semiconductor memory apparatus, memory access control system and data reading method - In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data. | 11-06-2008 |
| 20080278991 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line. | 11-13-2008 |
| 20080280415 | Method of manufacturing semiconductor memory device - A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a first electrode that is connected to the selection transistor, a variable resistance layer, and a second electrode; forming the capacitance element by sequentially laminating a third electrode that is connected to the separate selection transistor, a dielectric layer, and a fourth electrode; forming the dielectric layer and the variable resistance layer with a mutually identical material; forming either one of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode; and forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode. | 11-13-2008 |
| 20080291762 | SEMICONDUCTOR MEMORY DEVICE FOR PRECHARGING BIT LINES EXCEPT FOR SPECIFIC READING AND WRITING PERIODS - A semiconductor memory device includes a memory cell having an FET of a floating body type, and a capacitor for storing a data charge; a bit line to which the source or the drain of the FET is connected; a precharging device for performing precharge control so that the bit line has a predetermined precharge voltage; a sense amplifier for amplifying and storing the potential of the bit line, which is set in accordance with the data charge read from the memory cell; a switching device, provided between the bit line and the sense amplifier, for performing selective connection therebetween; and a control part for controlling the precharging device, the sense amplifier, and the switching device. Except for each period for performing data reading or writing, the control part makes the precharging device perform the precharge control and makes the switching device disconnect the bit line from the sense amplifier. | 11-27-2008 |
| 20080291764 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: word lines; global bit lines intersecting therewith; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each of which includes memory cells each having a vertical transistor structure connected to the local bit lines at a lower portion and each being formed at an intersection of the word line and the local bit line, and is arranged corresponding to each section of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line. | 11-27-2008 |
| 20080316839 | MEMORY CELL ARRAY AND METHOD OF CONTROLLING THE SAME - To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage. | 12-25-2008 |
| 20090003041 | Semiconductor memory device and read method thereof - A semiconductor memory device comprises a plurality of memory cells each capable of storing at least three different states; a first sense amplifier for amplifying a ternary potential read out in accordance with a state stored in a selected memory cell based on a comparison with a first reference potential; and a second sense amplifier for amplifying a ternary potential read out in accordance with a state stored in the selected memory cell based on a comparison with a second reference potential. In the semiconductor memory device, the ternary potential comprises a high potential, a medium potential and a low potential, the first reference potential is set between the low potential and the medium potential, and the second reference potential is set between the high potential and the medium potential. | 01-01-2009 |
| 20090059644 | Semiconductor memory device having vertical transistors - A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided. | 03-05-2009 |
| 20090100220 | Memory system, control method thereof and computer system - A memory system includes a memory cell array for storing data; and a register unit including one or more registers for storing system information. In the memory system, when a simultaneous access to the memory cell array and the register unit is requested, write data for the memory cell array is inputted after write data for the register unit is inputted, respectively through a common data input bus in a write operation, and read data from the memory cell array is outputted after read data from the register unit is outputted, respectively through a common data output bus in a read operation. | 04-16-2009 |
| 20090103389 | Semiconductor memory device and method of providing product families of the same - Disclosed is a semiconductor memory device including a plurality of banks, a plurality of data input/output terminals, control signal terminals, address signal terminals, and at least one or a plurality of virtual chips, each of which has the banks grouped together, thereby being operable as one independent chip. Each of the data input/output terminals are allocated in dedicated manner to the one virtual chip or one of the plurality of virtual chips. The control signal terminals and the address signal terminals are shared among the one or the plurality of virtual chips. | 04-23-2009 |
| 20090164728 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM USING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a data storage region which includes a plurality of unit data regions storing data, an information storage region which includes a plurality of unit information regions each storing information related to the data stored in associated one of the unit data regions, and an address generation circuit which generates an address designating one of the unit data regions and one of the unit information regions associated with each other. | 06-25-2009 |
| 20090240866 | Multi-port memory and computer system provided with the same - A multi-port memory, comprising: m (m≧2) input/output ports independent of one another; n (n≧2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1≦p≦m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks. | 09-24-2009 |
| 20090240897 | Multi-port memory and system using the same - A multi-port memory, comprising: a memory array made of a plurality of memory cells arranged at intersection points between a plurality of bit lines and a plurality of word lines, the memory array being divided into n (an integer of 2 or greater) memory banks; m (an integer of 2 or greater) input/output ports, each independently performing input and output of a command, an address, data to and from each of the memory banks; and a route switching circuit that sets signal for the command, address, and data between the memory banks and the input/output ports, the route switching circuit controlling a connection state of signal lines between the plurality of input/output ports and the plurality of memory banks. | 09-24-2009 |
| 20090251947 | Semiconductor device having single-ended sensing amplifier - A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage. | 10-08-2009 |
| 20090251948 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes. | 10-08-2009 |
| 20090257268 | Semiconductor device having single-ended sensing amplifier - A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal reading from the memory cell is reduced, wherein the amplifier amplifies a signal outputted from an input/output terminal through the use of a single MOS transistor that has a single-ended structure. | 10-15-2009 |
| 20090257298 | Semiconductor device having single-ended sensing amplifier - A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit line, and a global bit line voltage determination circuit; and at least the ON/OFF timing of the second MOS transistor or the read timing of a global sense amplifier that includes the global bit line voltage determination circuit is controlled by the output signal of a delay circuit that includes a replica of the first MOS transistor and a replica of the global bit line voltage determination circuit. | 10-15-2009 |
| 20090268537 | Semiconductor memory device - A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory. | 10-29-2009 |
| 20100054016 | Semiconductor memory device having floating body type NMOS transistor - A semiconductor memory device comprises a memory cell array and a sense amplifier circuit. The memory cell array includes a first NMOS transistor which has a gate electrode connected to a word line and has one source/drain region connected to a bit line. The sense amplifier circuit includes a second NMOS transistor which has a gate electrode connected to the bit line and has one source/drain region connected to a predetermined voltage. In the semiconductor memory device, each of the first and second MOS transistors is a floating body type NMOS transistor, and the predetermined voltage is supplied to the bit line at least in a precharge operation, thereby preventing characteristic deterioration due to accumulation of holes in the floating body. | 03-04-2010 |
| 20100054065 | Sense amplifier circuit and semiconductor memory device - A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell. | 03-04-2010 |
| 20100054066 | Memory device, semiconductor memory device and control method thereof - A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation. | 03-04-2010 |
| 20100061170 | Sense amplifier circuit and semiconductor memory device - A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor supplies a predetermined voltage to the bit line and switches connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor having a gate connected to the sense node amplifies a signal transmitted from the bit line via the first MOS transistor. The first voltage setting circuit sets the bit line to a first voltage, and the second voltage setting circuit sets the sense node to a second voltage. In the sense amplifier circuit, after setting the bit line and the sense node to respective voltages, the bit line is driven in a charge distributing mode via the first MOS transistor so that a signal voltage at the sense node is amplified by the second MOS transistor. | 03-11-2010 |
| 20110063891 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR SYSTEM - A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line. | 03-17-2011 |
| 20110063892 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 03-17-2011 |
| 20110063935 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 03-17-2011 |
| 20110134678 | Semiconductor device having hierarchical structured bit line - A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained. | 06-09-2011 |
| 20110164460 | Semiconductor device and method of controlling the same - A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks. | 07-07-2011 |
