Patent application number | Description | Published |
20080290341 | STACKED SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - A stacked semiconductor device includes: an internal circuit; a through electrode provided to penetrate through a semiconductor substrate; a test wiring to which a predetermined potential different from a substrate potential is supplied at a time of a test; a first switch arranged between the through electrode and the internal circuit; a second switch arranged between the through electrode and the test wiring; and a control circuit that exclusively turns on the first and the second switches. Thereby, it becomes possible to perform an insulation test in a state that the through electrode and the internal circuit are cut off. Thus, even when a slight short-circuit that does not lead to a current defect occurs, the short circuit can be detected. | 11-27-2008 |
20090153177 | SEPARATE TESTING OF CONTINUITY BETWEEN AN INTERNAL TERMINAL IN EACH CHIP AND AN EXTERNAL TERMINAL IN A STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device is disclosed which is capable of conducting a test to determine whether or not there is continuity between an external terminal and a corresponding internal terminal in each chip, on an internal terminal-in each chip basis. The semiconductor device includes continuity test dedicated terminals for each chip, and continuity test elements each connected between an internal terminal in each chip and a continuity test dedicated terminal associated with the chip. A voltage is applied between an external terminal associated with an internal terminal whose connection status is to be checked and a continuity test dedicated terminal associated with a chip which includes the internal terminal such that a continuity test element associated with the internal terminal is rendered conductive. Thereafter, the value of current that flows through the continuity test element is measured to determine the connection status of the internal terminal. | 06-18-2009 |
20090294990 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 12-03-2009 |
20090303770 | Memory chip and semiconductor device - A memory chip is provided, including internal signal/data terminals disposed in a central part of the memory chip and memory cell arrays arranged around the internal terminals to surround the same and electrically connected thereto. A semiconductor device is also provided, having a memory chip and a logic chip stacked with an interposer interposed therebetween. The logic chip has internal signal/data terminals disposed in its central part and electrically connected to the memory chip. The memory chip includes internal signal/data terminals disposed in its central part, and memory arrays arranged around the internal terminals to surround the same and connected thereto. The internal terminals of the logic chip are connected to the internal terminals of the memory chip via through holes (through electrodes) in the interposer. | 12-10-2009 |
20100193962 | SEMICONDUCTOR DEVICE - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 08-05-2010 |
20100232201 | STACKED SEMICONDUCTOR MEMORY DEVICE - A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes. | 09-16-2010 |
20110084385 | Semiconductor device and information processing system including the same - A semiconductor device includes a plurality of core chips and an interface chip that controls the core chips. Each of the core chips and the interface chip includes plural through silicon vias that penetrate a semiconductor substrate and plural pads respectively connected to the through silicon vias. The through silicon vias include a through silicon via of a power source system to which a power source potential or a ground potential is supplied, and a through silicon via of a signal system to which various signals are supplied. Among the pads, at least an size of a pad connected to the through silicon via of the power source system is larger than a size of a pad connected to the through silicon via of the signal system. Therefore, a larger parasitic capacitance can be secured. | 04-14-2011 |
20110084404 | Semiconductor device - One interface chip and a plurality of core chips are stacked, and these semiconductor chips are electrically connected to each other via a plurality of through silicon vias. A data signal output from a driver circuit is input into the core chip via one of the through silicon vias. An output selection circuit selects any one of the through silicon vias by activating a corresponding one of a plurality of tri-state inverters. When an inverter is activated, a primary selection circuit causes a test signal to be supplied to a receiver circuit from a test pad. When the inverter is inactivated, a data signal from any one of the through silicon vias is supplied to the receiver circuit. | 04-14-2011 |
20110084758 | Semiconductor device - To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced. | 04-14-2011 |
20110093224 | Semiconductor device, semiconductor device testing method, and data processing system - To include one or a plurality of internal signal lines that electrically connects an interface chip to a core chip. The interface chip includes a first circuit that outputs a current to an internal wiring and the core chip includes a second circuit that outputs a current to the first internal signal line. The interface chip includes a determination circuit that has a first input terminal connected to the internal wiring through which the current outputted by the first circuit flows and a second input terminal connected to an end of the first internal signal line in the interface chip, and outputs a voltage according to a potential difference between a voltage of the first input terminal and a voltage of the second input terminal. | 04-21-2011 |
20110104852 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 05-05-2011 |
20120122251 | STACKED TYPE SEMICONDUCTOR MEMORY DEVICE AND CHIP SELECTION CIRCUIT - A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them. | 05-17-2012 |
20120305917 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip that includes a driver circuit, a second semiconductor chip that includes a receiver circuit and an external terminal, and a plurality of through silicon vias that connect the first semiconductor chip and the second semiconductor chip. The first semiconductor chip further includes an output switching circuit that selectively connects the driver circuit to any one of the through silicon vias, the second semiconductor chip further includes an input switching circuit that selectively connects the receiver circuit to any one of the through silicon vias and the external terminal, the input switching circuit includes tri-state inverters each inserted between the receiver circuit and an associated one of the through silicon vias and the external terminal, and the input switching circuit activates any one of the tri-state inverters. | 12-06-2012 |
20130011967 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips. | 01-10-2013 |
20130175682 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film. | 07-11-2013 |
20130187294 | SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 07-25-2013 |
20130234342 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor chip including a plurality of driver circuits and an output switching circuit coupled to the plurality of driver circuits. The device also includes a second semiconductor chip and a plurality of through silicon vias provided on at least one of the first and second semiconductor chips. The output switching circuit is coupled between the plurality of driver circuits and the plurality of the through silicon vias, and outputs each of signals from the plurality of driver circuits to corresponding one of the plurality of through silicon vias. | 09-12-2013 |
20140073127 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure. | 03-13-2014 |
20140320203 | SEMICONDUCTOR DEVICE - A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias | 10-30-2014 |