Patent application number | Description | Published |
20110307850 | RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 12-15-2011 |
20120159414 | Simultaneous Multi-Corner Static Timing Analysis Using Samples-Based Static Timing Infrastructure - A method of performing simultaneous multi-corner static timing analysis (STA) on a design for an integrated circuit is provided. This method can include reading design data including a netlist, parasitics, and libraries at a plurality of corners. Each corner can represent a set of process, temperature, and voltage conditions. Using the design data as inputs, a plurality of operations can be performed to generate timing reports regarding the design at the plurality of corners. Notably, each operation has a single control flow and uses vectors of samples for performing the plurality of operations. Each sample is a value associated with a corner. This method minimizes computational resource and memory usage as well as accelerates the turn around time of multi-corner analysis. | 06-21-2012 |
20120278647 | Reducing Memory Used To Store Totals In Static Timing Analysis - A system and a method are disclosed for reducing memory used in storing totals during static timing analysis. Totals are stored at various points along paths analyzed in static timing analysis. Some totals may not be merged for reasons including differing clock re-convergence pessimism removal (CRPR) dominators, exceptions, or clocks. Totals at a point may be stored in a super-tag mapping table and replaced at the point with a super-tag. The super-tag includes a super-tag ID referencing the totals stored in the super-tag mapping table. The super-tag also includes a time delay value. The time delay value allows the super-tag ID to be reused in other super-tags at other points while still storing total time delays at the other points. Therefore, the memory used to store totals is reduced in many situations. | 11-01-2012 |
20120278778 | Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis - A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete. | 11-01-2012 |
20130227507 | Recursive Hierarchical Static Timing Analysis - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 08-29-2013 |
20130246991 | Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis - A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete. | 09-19-2013 |