Inventors list |
Assignees list |
Classification tree browser |
Top 100 Inventors |
Top 100 Assignees |
Kayhan
Kayhan Goeney, Esslingen DE
| Patent application number | Description | Published |
|---|---|---|
| 20100063711 | METHOD AND DEVICE FOR CONTROLLING THE OPERATING MODE OF AN INTERNAL COMBUSTION ENGINE - The invention relates to a method for controlling the operating mode of an internal combustion engine ( | 03-11-2010 |
Kayhan Kucukcakar, Sunnyvale, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20080295053 | Characterizing Sequential Cells Using Interdependent Setup And Hold Times, And Utilizing The Sequential Cell Characterizations In Static Timing Analysis - A sequential cell is characterized using interdependent setup/hold time pairs to produce associated clock-to-Q delay values, and then identifying setup/hold time pairs that produce a selected clock-to-Q delay value (e.g., 10% of failure). The identified setup/hold time pairs (or a piecewise linear (PWL) approximation thereof) are then stored in a cell library for use in static timing analysis (STA). During STA, the setup and hold skews calculated for each synchronous circuit are compared with a selected setup/hold time pair stored in the cell library (e.g., a pair having a relatively low hold value). If at least one of the setup and hold skews violates the selected setup/hold time pair, then the remaining identified setup/hold time pairs (or the PWL approximation) are utilized to determine if the synchronous circuit is violates established constraints, and if not, to identify the setup and hold times required to remove the violation. | 11-27-2008 |
Kayhan Kucukcakar, Los Altos, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110307850 | RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 12-15-2011 |