Patent application number | Description | Published |
20120239844 | DATA STORAGE SYSTEM FOR MANAGING SERIAL INTERFACE CONFIGURATION BASED ON DETECTED ACTIVITY - According to one aspect, a data storage system is disclosed. In one embodiment, the data storage system includes a storage backplane having a plurality of drive slots configured to operatively connect to a corresponding plurality of mass storage devices, a first serial interface operative to communicatively connect one or more sets of the plurality of drive slots to a host bus adapter (HBA), according to a first drive slot assignment, a second serial interface operative to communicatively connect one or more sets of the plurality of drive slots to the HBA, according to a second drive slot assignment, and a backplane controller operatively connected to the first serial interface and the second serial interface, operative to detect the activity status on the first serial interface and the activity status on the second serial interface and, if a change in the activity status is detected for at least one of the first serial interface and the second serial interface, modify the first drive slot assignment and the second drive slot assignment. | 09-20-2012 |
20120239845 | BACKPLANE CONTROLLER FOR MANAGING SERIAL INTERFACE CONFIGURATION BASED ON DETECTED ACTIVITY - According to one aspect, a backplane controller of a storage backplane is disclosed, the storage backplane having a plurality of drive slots configured to operatively connect to a corresponding plurality of mass storage devices. In one embodiment, the backplane controller is operative to perform functions that include detecting activity status on a first serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to a host bus adapter (HBA), according to a first drive slot assignment. The backplane controller is further operative to detect an activity status on a second serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to the HBA, according to a second drive slot assignment. The backplane controller is also operative to, if a change in the activity status is detected for at least one of the first serial interface and the second serial interface, modify the first drive slot assignment and the second drive slot assignment. | 09-20-2012 |
20120246385 | EMULATING SPI OR 12C PROM/EPROM/EEPROM USING FLASH MEMORY OF MICROCONTROLLER - In one aspect, a microcontroller is disclosed. In one embodiment, the microcontroller includes a system memory that has an erasable memory of a first type, with a first storage partition and a second, different storage partition. The system memory also has a random access memory (RAM). The microcontroller further includes a network interface that is configured to communicate management commands over a communications link, and a programmable processor that is operatively connected to the system memory and the network interface. The communications link includes an interface bus and is configured for one or more of I2C, SPI, and system management bus communications. The programmable processor is programmed to perform functions that include receiving a first management command configured for the erasable memory of the first type, causing the second storage partition of the erasable memory of the first type to emulate a second type of erasable memory, and receiving a second management command configured for the second type of erasable memory. | 09-27-2012 |
20130080697 | DRIVE MAPPING USING A PLURALITY OF CONNECTED ENCLOSURE MANAGEMENT CONTROLLERS - According to one aspect, a computing system having a plurality of enclosure management controllers (EMCs) is disclosed. In one embodiment, the EMCs are communicatively coupled to each other and each EMC is operatively connected to a corresponding plurality of drive slots and at least one of a plurality of drive slot status indicators. Each EMC is operative to receive enclosure management data, detect an operational status of the drive slots, and generate drive slot status data. One of the EMCs is configured to function at least partly as a master EMC to receive drive slot status data and, based on received enclosure management data and received drive slot status data, generate mapped data for each one of the EMCs for selectively activating at least one of the drive slot status indicators to indicate corresponding operational status. | 03-28-2013 |
20150100298 | TECHNIQUES FOR VALIDATING FUNCTIONALITY OF BACKPLANE CONTROLLER CHIPS - Present disclosure relates to a system for validating target backplane controller chips. The system includes a backplane controller chip validation board. In certain embodiments, the backplane controller chip validation board includes: (a) a program/verify/validate controller chip, (b) one or more backplane controller chip sockets for installing one or more target backplane controller chips, and (c) a backplane simulator. The program/verify/validate controller chip includes backplane controller chip firmware verification software, a USB interface, and a software storage. The backplane simulator is used to simulate functions of drives, LEDs, and other devices of a backplane for verifying all functions of target backplane controller chips. The backplane controller chip validation board is in communication with a host computer, and the host computer has a user interface, a backplane controller chip validation software, a USB interface, and a software storage to store backplane controller chip firmware. | 04-09-2015 |
20150100299 | TECHNIQUES FOR PROGRAMMING AND VERIFYING BACKPLANE CONTROLLER CHIP FIRMWARE - Present disclosure relates to a system for programming and verifying backplane controller chip firmware on target backplane controller chips. The system includes a backplane controller chip validation board. In certain embodiments, the backplane controller chip validation board includes: (a) a program/verify/validate controller chip, (b) one or more backplane controller chip sockets for installing one or more target backplane controller chips, and (c) a backplane simulator. The program/verify/validate controller chip includes backplane controller chip firmware verification software, a USB interface, and a software storage. The backplane simulator is used to simulate functions of drives, LEDs, and other devices of a backplane for verifying all functions of backplane controller chip firmware. The backplane controller chip validation board is in communication with a host computer, and host computer has a user interface, a backplane controller chip programming and verifying software, a USB interface, and a software storage to store backplane controller chip firmware. | 04-09-2015 |
20150149684 | HANDLING TWO SES SIDEBANDS USING ONE SMBUS CONTROLLER ON A BACKPLANE CONTROLLER - Present disclosure relates to a computer-implemented method for handling two SES sidebands using one SMBUS controller. The method includes one or more of following operations: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data from host computer for monitoring and controlling at least one drive of first and second group of drives, (c) determining address and device number of drive to which received control commands and control data are directed, (d) forwarding control commands and control data to first or second SMBUS sideband handler based on address received, (e) controlling the blinking of the LEDs of the drive by first or second SMBUS sideband handler, (f) generating responses by the first or second SMBUS sideband handler, (g) receiving responses by the SMBUS controller, and (h) sending the responses back to the host computer within a predetermined time period. | 05-28-2015 |
20150161069 | HANDLING TWO SGPIO CHANNELS USING SINGLE SGPIO DECODER ON A BACKPLANE CONTROLLER - An aspect of present disclosure relates to a computer-implemented method for handling two SGPIO channels by using one SGPIO decoder. The method includes: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data for monitoring and controlling a first and a second group of drive slots, (c) checking a clock signal having a first time period and a second time period, (d) forwarding the control commands and control data for the first group to the first group of drive slots during first time period, and forwarding the control commands and control data for the second group to the second group of drive slots during second time period, (e) receiving responses from first and second group of drive slots, respectively, and (f) sending the responses from first and second group of drive slots to the host computer. | 06-11-2015 |