Patent application number | Description | Published |
20130086335 | MEMORY SYSTEM AND MEMORY INTERFACE DEVICE - A memory access source regards a plurality of memory circuits as single memory circuit and transmits a row address and a column address in time division to an access control circuit. The access control circuit performs a speculative access to the plurality of memory circuits when receiving the row address, and performs an access to a memory circuit which is specified by the column address after receiving the column address and sends a cancel command of the speculative access to the other memory circuit out of target. Or, in the case of read access, the access control circuit receives read data from the plurality of memory circuits and discards the read data of the memory circuit out of the target by the column address. | 04-04-2013 |
20130166860 | MEMORY ACCESS CONTROL DEVICE AND COMPUTER SYSTEM - A memory interleaving device accesses a memory in an interleaved manner for changing the number of ways of interleaving during system operation. During a copy which changes a first configuration before changing the number of ways in the interleaving to a second configuration after changing the number of ways in the interleaving, a memory access control device reads the memory in the first configuration before changing the number of ways of the interleaving for an external read request and writes the memory in both of the first configuration before changing the number of ways in the interleaving and the second configuration after changing the number of ways in the interleaving for an external write request. | 06-27-2013 |
20130212333 | INFORMATION PROCESSING APPARATUS, METHOD OF CONTROLLING MEMORY, AND MEMORY CONTROLLING APPARATUS - An information processing apparatus provided with a plurality of nodes each including at least one processor, a system controller, and a main memory, includes a status storage unit that stores statuses of a plurality of cache lines and that is capable of reading statuses of a plurality of cache lines by one reading operation, a recording unit that is provided in a system controller in at least one node and that records all or part of the statuses stored in the status storage unit, wherein the system controller records obtained statuses in the recording unit on a condition that all of the statuses of the plurality of cache lines obtained by reading the status storage unit are invalid statuses or shared statuses in different nodes when the system controller has read the status storage unit in response to a request. | 08-15-2013 |
20130305007 | MEMORY MANAGEMENT METHOD, MEMORY MANAGEMENT DEVICE, MEMORY MANAGEMENT CIRCUIT - A memory management method includes extracting a physical address in which an error has been detected from a conversion table. The memory management method includes extracting, when a physical address that indicates a storage area that stores therein information that is to be deleted due to the occurrence of the detected error is acquired from the information processing apparatus, the memory address associated with the acquired physical address from the conversion table, performed by the memory management device. The memory management method includes updating the conversion table such that the extracted memory address is associated in the conversion table with the extracted physical address, performed by the memory management device. The memory management method includes moving the information stored in the storage area indicated by the extracted physical address to the storage area indicated by the extracted memory address. | 11-14-2013 |
Patent application number | Description | Published |
20080296551 | RESISTANCE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes. | 12-04-2008 |
20090121823 | VARIABLE-RESISTANCE ELEMENT - The invention provides a variable-resistance element having a multilayer structure. The variable-resistance element includes, for example, a first electrode, a second electrode, and an oxygen ion migration layer disposed between the first electrode and the second electrode. In the oxygen ion migration layer, oxygen vacancy can be produced owing to oxygen ion migration, thereby forming a low resistance path. The variable-resistance element also includes an oxygen ion generation promoting layer disposed between the oxygen ion migration layer and the first electrode and held in contact with the oxygen ion migration layer. | 05-14-2009 |
20090218565 | RESISTANCE VARIABLE ELEMENT - A resistance variable element is provided, which is capable of performing bipolar operation by a specified mechanism and usable as a memory. The resistance variable element has a laminated structure including an electrode, an electrode, an oxide layer between the electrodes, and an oxide layer in contact with the oxide layer between the oxide layer and the electrode. The oxide layer is switchable from the low-resistance state to the high-resistance state by donating oxygen ions to the oxide layer, and from the high-resistance state to the low-resistance state by accepting oxygen ions from the oxide layer. The oxide layer is switchable from the low-resistance state to the high-resistance state by accepting oxygen ions from the oxide layer, and from the high-resistance state to the low-resistance state by donating oxygen ions to the oxide layer. | 09-03-2009 |
20100200832 | RESISTANCE VARIABLE ELEMENT - A resistance variable device is provided, which is capable of making a bipolar operation based on a predetermined operation principle. The resistance variable device is usable as a storage device. The resistance variable device has a laminated structure which include, for example, a first electrode, a second electrode, and a hole conductive layer between the first and second electrodes. The hole conductive layer gives anions to the second electrode, thereby changing its state from a reference electric field state to a positive electric field state. The hole conductive layer also receives anions from the second electrode, thereby changing its state from the positive electric field state to the reference electric field state. | 08-12-2010 |
20110073833 | RESISTANCE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME - A resistance memory element having a pair of electrodes and an insulating film sandwiched between a pair of electrodes includes a plurality of cylindrical electrodes of a cylindrical structure of carbon formed in a region of at least one of the pair of electrodes, which is in contact with the insulating film. Thus, the position of the filament-shaped current path which contributes to the resistance states of the resistance memory element can be controlled by the positions and the density of the cylindrical electrodes. | 03-31-2011 |
Patent application number | Description | Published |
20080198939 | Transmitter circuit and radio transmission apparatus for transmitting data via radio by using impulses - A transmitter circuit, which transmits data by using an impulse, has a variable delay circuit and a logic circuit. The variable delay circuit takes a clock as an input, and delays the clock in accordance with the data. The logic circuit takes the clock and an output of the variable delay circuit as inputs, and outputs an impulse by performing a logic operation between the clock and the output of the variable delay circuit. | 08-21-2008 |
20110163824 | ELECTRONIC CIRCUIT AND ELECTRONIC DEVICE - An electronic circuit includes a first inductor, a second inductor that is magnetically coupled with the first inductor, induced current flowing through the second inductor by a magnetic field generated by the first inductor, and a current changing part that is connected to the second inductor and is configured to change the induced current that flows through the second inductor. | 07-07-2011 |
20120139632 | DIFFERENTIAL AMPLIFIER CIRCUIT - A differential amplifier circuit includes a first/second field effect transistor including a gate coupled to a first/second differential input signal terminal, a source coupled to a reference potential node, and a drain coupled to a first/second differential output signal terminal, a first variable capacitor coupled between the gate of the first field effect transistor and the drain of the second field effect transistor, a second variable capacitor coupled between the gate of the second field effect transistor and the drain of the first field effect transistor, and a first envelope detector configured to detect an envelope of a signal at the first differential output signal terminal or the second differential output signal terminal, the first variable capacitor and/or the second variable capacitor has a capacitance that varies in accordance with an envelope detected by the first envelope detector. | 06-07-2012 |
Patent application number | Description | Published |
20100228930 | ACCESS CONTROL DEVICE, INFORMATION PROCESSING DEVICE, ACCESS CONTROL PROGRAM AND ACCESS CONTROL METHOD - An access control device which writes data to each of predetermined storage block sets in a storage device of which a storage area has been divided into a plurality of storage blocks. The control device includes a management information storage section and an access processing section. The management information storage section stores, for each of said storage blocks, record enable/disable information indicating whether said storage block is a non-defective block in which the data can be recorded or a defective block in which the data cannot be recorded. If the data is written to each of said storage block sets, the access processing section writes the data only to non-defective blocks in said storage block set based on the record enable/disable information stored in said management information storage section. | 09-09-2010 |
20100241806 | DATA BACKUP METHOD AND INFORMATION PROCESSING APPARATUS - An information processing apparatus includes, a first storage unit, a second storage unit in which data stored in the first storage unit is backed up, and a memory controller that controls data backup operation. The memory controller divides a transfer source storage area into portions, and provides two transfer destination areas, each of the two transfer destination areas being divided into portions, backs up data in a direction from a beginning address of each divided area of the transfer source storage area to an end address thereof in one of the transfer destination areas provided for each divided area of the transfer source storage area, and backs up data in a direction from the end address of each divided area of the transfer source storage area to the beginning address thereof in the other transfer destination storage area. | 09-23-2010 |
20100299565 | CONTROLLING APPARATUS AND CONTROLLING METHOD - A controlling apparatus for controlling a disk array unit includes a cache memory for caching data of the disk array unit; a nonvolatile memory for storing the data in the cache memory; and a control unit for detecting a defective location in the nonvolatile memory where the data is stored defectively and updating information indicating the defection location, for generating an error detection code of the updated information, for writing the generated information and the associated error detection code into an area of the nonvolatile memory different from any area where any information indicating any defective location previously detected and stored into the nonvolatile memory, and for controlling writing the data in the cache memory into a location of the nonvolatile memory designated by any selected one of the information stored in the nonvolatile memory. | 11-25-2010 |
20100306570 | ASYNCHRONOUS INTERFACE CIRCUIT AND DATA TRANSFER METHOD - An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and transferring data of the data stream in synchronism with a first clock signal, and holding the received data until an input of a next data, an asynchronous memory for sequentially receiving the data held in the data holding circuit in synchronism with the first clock signal and for outputting the data in the order of inputting in synchronism with a second clock signal. The asynchronous interface circuit further includes a monitor for detecting an operating state of the asynchronous memory, and a selector for selecting one of the data output from the asynchronous memory and the data output from the data holding circuit on the basis of a detecting result of the monitor. | 12-02-2010 |
20100306586 | Storage apparatus and method of data processing - A storage apparatus includes a backup processing unit that stores data stored in a first memory into a second memory as backup data upon occurrence of a power failure, a restore processing unit that upon recovery from the power failure restores the backup data backed up in the second memory to the first memory and erases the backup data, and an erasure processing termination unit that terminates the erasure processing upon a power failure occurring during erasure processing for erasing the backup data stored in the second memory, and a re-backup processing unit that re-backs up data in the first memory corresponding to the backup data erased from the second memory before the erasure processing is terminated by the erasure processing termination unit to a location in the second memory subsequent to a last location that contains the backup data which has not been erased. | 12-02-2010 |
20100318844 | BACKUP METHOD AND DISK ARRAY APPARATUS - A backup method makes a backup of cache data to a nonvolatile memory by using a controller, the cache data being stored in the volatile memory. The backup method includes writing the cache data stored in the volatility memory in a selected area of the nonvolatile memory, generating party data by operating the parity operations between each of the predetermined parts of the cache data in the volatile memory, verifying whether an error found in the part of the cache data in the nonvolatile memory can be recovered by using the parity data, and rewriting the part of the cache data when the error found in the part of the cache data in the nonvolatile memory cannot be recovered by using the parity data in an area of the nonvolatile memory different from the selected area. | 12-16-2010 |
20110010499 | STORAGE SYSTEM, METHOD OF CONTROLLING STORAGE SYSTEM, AND METHOD OF CONTROLLING CONTROL APPARATUS - A storage system including a storage, has a first power supplier for supplying electronic power, a second power supplier for supplying electronic power when the first power supplier not supplying electronic power to the storage system, a cache memory for storing data sent out from a host, a non-volatile memory for storing data stored in the cache memory, and a controller for writing the data stored in the cache memory into the non-volatile memory when the second supplier supplying electronic power to the storage system, for stopping the writing and for deleting data stored in the non-volatile memory so until a free space volume of the non-volatile memory being not less than a volume of the data stored in the cache memory when the first supplier restoring electronic power to the storage system. | 01-13-2011 |
20110314236 | Control apparatus, control method, and storage system - In a control apparatus, a write control unit controls operation of writing data to a non-volatile storage unit. The write control unit is configurable with given control data. A control data storage unit stores first control data for the write control unit. An input reception unit receives second control data for the write control unit. A configuration unit configures the write control unit with the first control data stored in the control data storage unit when the first control data has a newer version number than that of the second control data received by the input reception unit, and with the second control data when the second control data has a newer version number than that of the first control data. | 12-22-2011 |
20120005436 | CONTROL DEVICE, CONTROLLER MODULE, AND CONTROL METHOD - A control device including: a storage device that includes a first storage area including a plurality of blocks into which data can be written more than once and a second storage area into which data can be written only once, wherein the first storage area further stores a flag for each of the blocks, the flag indicating whether or not the block is allowed to be used; a flag management information creation unit configured to create, on the basis of the flag, a flag management information for managing whether or not data can be stored in each block of the storage device; and a management information controller configured to cause the flag management information to be stored in the second storage area. | 01-05-2012 |
20120072684 | STORAGE APPARATUS AND CONTROLLING METHOD - A storage apparatus includes a storage medium configured to store data and a control unit configured to control access to the storage medium. The control unit includes first storage configured to store data to be stored in the storage medium, a second storage configured to store data, a control information generator configured to generate control information indicating a storage state of the data in the first storage and a transfer controller configured to control transfer of the data stored in the first storage to the second storage on the basis of the control information generated by the control information generator when the supply of power to the control unit is stopped. | 03-22-2012 |
20120144268 | ACCESS CONTROL APPARATUS, STORAGE APPARATUS, AND METHOD - An access control apparatus for controlling an access to a storage device, the access control apparatus includes a measuring unit configured to measure the time to erase data stored in the storage device, and a determination unit configured to determine a data size of an error correcting code added to data stored in the storage device in accordance with the time measured by the measuring unit. The access control apparatus includes a generation unit configured to generate the error correcting code having the data size determined by the determination unit, and an access controller configured to write the data and the error correcting code generated by the generation unit into the storage device. | 06-07-2012 |
20120254636 | CONTROL APPARATUS AND CONTROL METHOD - A control apparatus includes a capacitor to store electric power supplied from the power supply unit and to supply the stored electric power to the control apparatus when the power supply from the power supply unit is stopped, a first nonvolatile memory, a second nonvolatile memory, a first controller, and a second controller. The first controller writes the data, stored in the cache memory, into the first nonvolatile memory when the external power supply is stopped verifies whether the data stored in the first nonvolatile memory is normal, and sends information of area where the data in the first nonvolatile memory is not normal when the verification indicates that the writing is not normal. And the second controller writes the information sent from the first controller into the second nonvolatile memory. | 10-04-2012 |