Patent application number | Description | Published |
20110231369 | STORAGE CONTROLLER FOR MIRRORING DATA WRITTEN TO CACHE MEMORY AREA - A first controller has a first CM area having a plurality of first sub-areas, and a second controller has a second CM area having a plurality of second sub-areas. The first controller stores first data in any of the first sub-areas, and in addition, stores a mirror of the first data (first mirror data) in any of the second sub-areas. The first controller manages a pair (an association relationship) of the storage-destination first sub-area of the first data and the storage-destination second sub-area of the first mirror data. Similarly, the second controller stores second data in any of the second sub-areas, and in addition, stores a mirror of the second data (second mirror data) in any of the first sub-areas. The second controller manages a pair (an association relationship) of the storage-destination second sub-area of the second data and the storage-destination first sub-area of the second mirror data. | 09-22-2011 |
20120072641 | SEMICONDUCTOR STORAGE DEVICE AND DATA CONTROL METHOD THEREOF - The flash memory controller compresses data in response to a write request. On condition that there is a compression effect with respect to the compressed data, the flash memory controller writes the compressed data to the base area of a physical block of a flash memory. As physical pages assigned to the physical block, the flash memory controller reduces the physical pages assigned to the base area from 102 down to 59, and increases the physical pages assigned to the update area from 26 up to 69. Therefore, it is possible to suppress exhaustion of physical pages which are assigned to the update area, to reduce the number of erases of the physical block, and to consequently prolong device operating life. | 03-22-2012 |
20120102260 | STORAGE APPARATUS AND DATA CONTROL METHOD - Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. | 04-26-2012 |
20130086304 | STORAGE SYSTEM COMPRISING NONVOLATILE SEMICONDUCTOR STORAGE MEDIA - Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk. | 04-04-2013 |
20130091320 | STORAGE SYSTEM AND STORAGE METHOD - A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals. | 04-11-2013 |
20130311707 | STORAGE CONTROL APPARATUS AND STORAGE CONTROL METHOD - A storage control apparatus comprises a storage unit, an association unit, and an execution unit. The storage unit stores association information showing multiple physical chunks which are configured in a physical address space of a nonvolatile semiconductor memory, multiple logical storage areas which are configured in a logical address space of the nonvolatile semiconductor memory, multiple logical chunks which are respectively associated with the multiple physical chunks, and an association between a logical storage area and a logical chunk. The association unit changes the association by changing the association information in accordance with a state of the nonvolatile semiconductor memory, and identifies based on the association information a physical storage area corresponding to a logical storage area specified in an input/output request from a computer. The execution unit executes the input/output request with respect to the identified physical storage area. | 11-21-2013 |
20140321208 | DE-DUPLICATION IN FLASH MEMORY MODULE - Data capacity efficiency is improved by de-duplicating data assigned with a code that is different for each data. A storage apparatus comprising a flash memory control device equipped with one or more flash memory modules, wherein the flash memory module comprises at least one flash memory chip for providing a storage area, and a controller for controlling writing/reading of data including user data and a guarantee code accompanying the user data to and from the storage area provided by the flash memory chip, wherein the controller respectively divides a plurality of the data having the common user data into the user data and the guarantee code, stores one of the user data in an area of a predetermined unit of the storage area, and links and stores each of the guarantee codes accompanying the plurality of user data in an area of a predetermined unit of the storage area. | 10-30-2014 |
20150127896 | STORAGE SYSTEM AND STORAGE METHOD - A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals. | 05-07-2015 |
Patent application number | Description | Published |
20100034026 | ERASE METHOD AND NON-VOLATILE SEMICONDUCTOR MEMORY - An erase method for a non-volatile memory device having a defined erase unit divided into first and second inner erase units includes; applying an erase voltage to at least one of the first and second inner erase units in accordance with respective states of corresponding first and second fail flags, after applying the erase voltage to the at least one of the first and second inner erase units, performing an erase verification on the at least one of the first and second inner erase units, and updating the at least one of the first and second fail flags in accordance with erase verification results. | 02-11-2010 |
20100135081 | NONVOLATILE MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array and a control circuit configured to control reading and programming operations for reading data from and inputting data to the memory cell array, respectively. The control circuit includes first and second units. The first unit is configured to count a number of bits having logic 0 or a number of bits having logic 1, to set a logic where the counted number is greater than n/2 as an initial state to regenerate programming data, and to perform a programming operation based on the regenerated data, when simultaneously programming the programming data of n bits input for a designated address. The second unit is configured to program a recognition bit for recognizing which of the logic 0 and the logic 1 the initial state of the memory cell of the designated address is in, when the programming operation is performed. | 06-03-2010 |
20110157960 | Nonvolatile Memory Devices and Related Methods and Systems - Nonvolatile memory devices are provided including a memory cell array having a plurality of stacked memory layers and a rectifier configured to select memory cells constituting each memory layer sharing a word line or a bit line with another adjacent memory layer. The nonvolatile memory devices including a word line driving unit configured to drive a first word line, connected to a first memory cell of a first memory layer to be read, at a first voltage level and drive a second word line, connected to a second memory cell of a second memory layer sharing a first bit line connected to the first memory cell, at a second voltage level. The nonvolatile memory device further includes a bit line biasing unit configured to bias the first bit line at the second voltage level and bias a second bit line, connected to a third memory cell of a third memory layer sharing the first word line, at the first voltage level. Related methods and systems are also provided herein. | 06-30-2011 |