| Patent application number | Description | Published |
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| 20080211561 | Clock Signal Generation Circuit and Semiconductor Device - The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal. | 09-04-2008 |
| 20080297320 | Semiconductor device and IC label, IC tag, and IC card provided with the semiconductor device - A charge accumulation circuit having a structure in which a capacitor is divided into a plurality of pieces and the divided capacitors are connected in parallel through switches is provided. The charge accumulation circuit controls the switch provided between the capacitors and thus can dynamically vary electrostatic capacitance of the charge accumulation circuit which applies a voltage to a constant voltage circuit. | 12-04-2008 |
| 20110261864 | SEMICONDUCTOR DEVICE - In a case where an ASK method is used for a communication method between a semiconductor device and a reader/writer, the amplitude of a radio signal is changed by data transmitted from the semiconductor device to the reader/writer when data is not transmitted from the reader/writer to the semiconductor device. Therefore, in some cases, the semiconductor device mistakes data transmitted from the semiconductor device itself for data transmitted from the reader/writer to the semiconductor device. The semiconductor device includes an antenna circuit, a transmission circuit, a reception circuit, and an arithmetic processing circuit. The antenna circuit transmits and receives a radio signal. The transmission circuit outputs to the reception circuit a signal showing whether or not the antenna circuit is transmitting the radio signal. | 10-27-2011 |
| 20120081186 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME - A semiconductor device includes an antenna circuit for receiving a wireless signal, a power supply circuit generating power by the wireless signal received by the antenna circuit, and a clock generation circuit to which power is supplied. The clock generation circuit includes a ring oscillator which self-oscillates and a frequency divider which adjusts frequency of an output signal of the ring oscillator in an appropriate range. A digital circuit portion is driven by a clock having high frequency accuracy, so that a malfunction such as an incorrect operation or no response is prevented. | 04-05-2012 |
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| 20110127525 | SEMICONDUCTOR DEVICE - An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×10 | 06-02-2011 |
| 20110127526 | NON-LINEAR ELEMENT, DISPLAY DEVICE INCLUDING NON-LINEAR ELEMENT, AND ELECTRONIC DEVICE INCLUDING DISPLAY DEVICE - A non-linear element (such as a diode) which includes an oxide semiconductor and has a favorable rectification property is provided. In a transistor including an oxide semiconductor in which the hydrogen concentration is 5×10 | 06-02-2011 |
| 20110133178 | SEMICONDUCTOR DEVICE - One object is to provide a p-channel transistor including an oxide semiconductor. Another object is to provide a complementary metal oxide semiconductor (CMOS) structure of an n-channel transistor including an oxide semiconductor and a p-channel transistor including an oxide semiconductor. A p-channel transistor including an oxide semiconductor includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer, and a source and drain electrode layers in contact with the oxide semiconductor layer. When the electron affinity and the band gap of an oxide semiconductor used for the oxide semiconductor layer in the semiconductor device, respectively, are χ (eV) and E | 06-09-2011 |
| 20110156022 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ε | 06-30-2011 |
| 20110194327 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a reading signal line connected to one of a source electrode and a drain electrode of the reading transistor so that a predetermined reading potential is supplied to the reading signal line, and then detecting a potential of the bit line. | 08-11-2011 |
| 20110194331 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - The number of wirings per unit memory cell is reduced by sharing a bit line by a writing transistor and a reading transistor. Data is written by turning on the writing transistor so that a potential of the bit line is supplied to a node where one of a source and drain electrodes of the writing transistor and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined amount of charge is held in the node. Data is read by using a signal line connected to a capacitor as a reading signal line or a signal line connected to one of a source and drain electrodes of the reading transistor as a reading signal line so that a reading potential is supplied to the reading signal line, and then detecting a potential of the bit line. | 08-11-2011 |
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| 20090005687 | ULTRASONIC IMAGING APPARATUS - An ultrasonic imaging apparatus includes an ultrasonic probe which captures 3D tomographic image data, a puncture needle which is attached to a puncture guide and introduced into a 3D region of a subject on which the 3D tomographic image data is captured, and an image processor which forms image data on an introduction sectional plane including an expected introduction path along which the introduction is expected. The image processor includes a monitor area setting device which sets, in a 3D memory area, a monitor memory area which corresponds to a planar monitor area in the 3D region which the expected introduction path penetrates, a penetration point detecting device which detects a point of penetration of the monitor area by the puncture needle according to tomographic image data, and a sectional plane position correcting device which corrects the position of the introduction sectional plane to include the penetration point. | 01-01-2009 |
| 20090030314 | ULTRASONIC IMAGING APPARATUS AND IMAGE PROCESSING APPARATUS - An ultrasonic imaging apparatus includes a 3D tomographic image data capturing device which captures 3D tomographic image data from a 3D region inside a subject, a region-of-interest setting device which sets a 3D region of interest corresponding to the 3D region in an image memory, a surface image extracting device which extracts data on a surface image, in the 3D region of interest, of a massive tissue included in the 3D region, a stereoscopic display generating device which generates stereoscopic display data, and a display device which displays the stereoscopic display data. The region-of-interest setting device displays a 2D tomographic image of a 2D region including the massive tissue on the display device, allows setting of a marker indicating a periphery of the massive tissue in the 2D tomographic image, and generates the 3D region of interest according to data on the marker's position. | 01-29-2009 |
