Patent application number | Description | Published |
20080211469 | STEP-DOWN CIRCUIT - A step-down circuit generates a second power supply lower than a first power supply. The step-down circuit includes an output terminal connected to a load circuit, an output transistor connected between the first power supply and the output terminal, and having a gate terminal connected to a first node, a monitor transistor connected between the first power supply and a second node, and having a gate terminal connected to the first node, and a feedback circuit which sets a gate voltage of the output transistor in accordance with a difference between a voltage obtained by dividing a voltage of the second node and a reference voltage. A size of the monitor transistor is changed in accordance with an operation mode of the load circuit. | 09-04-2008 |
20080285324 | SEMICONDUCTOR MEMORY DEVICE - Shunt regions are formed at certain intervals in a memory cell array region as extending in a second direction. The shunt regions each include a contact formed to connect a word line or a signal line wired in the same direction to another metal wire. Extension regions are each formed of an extension of the shunt region in the data cache array region. Data input/output lines extend in a first direction and transfer data on bit lines simultaneously via a data cache array. Sense circuits are arranged around the data cache array and connected to the data input/output lines respectively. The data input/output lines are divided at a certain interval in the first direction. The divided portions are connected to respective leads formed in the extension region in the longitudinal direction thereof and connected to the sense circuits via the leads. | 11-20-2008 |
20100188913 | SEMICONDUCTOR MEMORY DEVICE HAVING SENSE AMPLIFIER - A semiconductor memory device includes a memory cell array, a page buffer, a data line pair, a differential amplifier and a precharger. The memory cell array includes a plurality of pages in which a plurality of memory cells are arranged. The page buffer is formed adjacent to the memory cell array, and includes a plurality of sense amplifiers configured to temporarily hold page data read from the memory cells in the page. The data line pair is arranged in the page buffer and is connected to the sense amplifiers. The differential amplifier is configured to amplify a potential difference between lines of the data line pair. The precharger is configured to precharge the data line pair to a predetermined potential. At least one of the differential amplifier and the precharger is formed in the page buffer, and the at least one circuit is electrically connected to the data line pair. | 07-29-2010 |
20110205806 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border. | 08-25-2011 |
20110305089 | THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS - According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant. | 12-15-2011 |
20120250424 | SEMICONDUCTOR MEMORY DEVICE - A sense amplifier circuit is connected to a bit-line and senses and amplifies a signal read from a memory cell. A first data latch is connected to a sense amplifier via a first bus. A second data latch is connected to a second bus. A plurality of circuit groups are repeatedly provided in a first direction, each circuit group comprising one sense amplifier circuit and one first data latch. The second data latch is provided between the circuit groups and an input/output buffer. | 10-04-2012 |
20120250425 | SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY CONTROL METHOD - According to one embodiment, the semiconductor memory includes a memory cell array which includes memory cells to store data, a buffer circuit which includes latches, each of the latches including transistors as control elements and a flip-flop, and a control circuit which turns off the transistors to deactivate one or more of the latches. | 10-04-2012 |
20130214854 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME - Provided is a semiconductor device, including an electrode, a first insulator, a first semiconductor having a bandgap of 2 eV or greater, a second insulator, and a second semiconductor, which are stacked on one another, and at least further including one or more electrodes in contact with the first semiconductor and two or more electrodes in contact with the second semiconductor. | 08-22-2013 |