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Kasem
Michelle Kasem, Chula Vista, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110172209 | 3H-IMIDAZO[4,5-B]PYRIDIN-5-OL DERIVATIVES USEFUL IN THE TREATMENT OF GPR81 RECEPTOR DISORDERS - The present invention is directed to certain 3H-imidazo[4,5-b]pyridin-5-ol derivatives of Formula (Ia) and pharmaceutically acceptable salts thereof, which exhibit useful pharmacological properties, for example, as agonists of the GPR81 receptor. Also provided by the present invention are pharmaceutical compositions containing compounds of the invention, and methods of using the compounds and compositions of the invention in the treatment of GPR81 associated disorders, for example, dyslipidemia, atherosclerosis, atheromatous disease, hypertension, coronary heart disease, stroke, insulin resistance, impaired glucose tolerance, type 2 diabetes, syndrome X, obesity, psoriasis, rheumatoid arthritis, Crohn's disease, transplant rejection, multiple sclerosis, systemic lupus erythematosus, ulcerative colitis, type 1 diabetes and acne. | 07-14-2011 |
Mohammed Kasem, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100219519 | COMPLETE POWER MANAGEMENT SYSTEM IMPLEMENTED IN A SINGLE SURFACE MOUNT PACKAGE - A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink. | 09-02-2010 |
| 20110101525 | SEMICONDUCTOR DEVICE WITH TRENCH-LIKE FEED-THROUGHS - A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated. | 05-05-2011 |
Y. Mohammed Kasem, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090256246 | SEMICONDUCTOR PACKAGING TECHNIQUES - A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die. | 10-15-2009 |
| 20090278179 | CHIP SCALE SURFACE MOUNT PACKAGE FOR SEMICONDUCTOR DEVICE AND PROCESS OF FABRICATING THE SAME - A semiconductor package has contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on the front side of the dice, covering the exposed portions of the metal plate and extending to side edges of the dice. The metal layer may cover connection pads on the front side of the dice. A second set of scribe lines are made coincident with the first set. Therefore, the metal layer remains on the side edges of the dice coupling the front and the back. As a result, the package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice. | 11-12-2009 |
| 20100295152 | Precision high-frequency capacitor formed on semiconductor substrate - A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique. | 11-25-2010 |
