Karthikeyan
Karthikeyan Appuraj, Hyderabad IN
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20150233348 | DYNAMIC CUT-IN WIND SPEED FOR WIND TURBINES - The present subject matter is directed to a system and method for operating a wind turbine. More specifically, the system and method determines a dynamic cut-in wind speed for the wind turbine based on one or more environmental conditions. In one embodiment, the method includes providing a predetermined cut-in wind speed for the wind turbine based on at least one estimated environmental condition for a wind turbine site; determining one or more actual environmental conditions near the wind turbine for a predetermined time period at the wind turbine site; determining a variance between the at least one estimated environmental condition and the one or more actual environmental conditions; calculating a dynamic cut-in wind speed based on the variance; and, operating the wind turbine based on the dynamic cut-in wind speed so as to increase wind turbine operational efficiency. | 08-20-2015 |
Karthikeyan Avudaiyappan, Sunnyvale, CA US
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20100262751 | Memory Control Unit Mapping Physical Address to DRAM Address for a Non-Power-of-Two Number of Memory Ranks Using Lower Order Physical Address Bits - A processor for low rank addressing of processor memory with non-power-of-two ranks. The processor includes cores that receive access requests to the processor memory (e.g., one or more DIMMs). The processor includes a memory controller connected to the core(s) that generates an address to the processor memory. The generating of the address includes identifying select rank bits in the physical address, determining whether the select rank bits map to a rank that is absent, and, when the physical address maps to an absent rank, modifying the physical address to include a modified set of select rank bits that are mapped to one of the ranks present in the processor memory. The modifying of the physical address may include swapping the lower rank bits with a higher order set of bits in the physical address. The memory controller proceeds with PA to DA conversions with the modified physical address. | 10-14-2010 |
20110153928 | MEMORY UTILIZATION TRACKING - A hardware memory control unit that includes a register block and hardware logic. The register block includes, for a hardware memory segment, an access count register for storing an access count, a low threshold register for storing a low threshold, and a high threshold register for storing a high threshold. The hardware logic includes functionality to increment the access count stored in the access count register for each memory access to the hardware memory segment performed during a predefined duration of time, and, at the end of the predefined duration of time, perform a response action when the access count stored in the access count register is less than the low threshold stored in the low threshold register, and perform a response action when the access count stored in the access count register is greater than the high threshold stored in the high threshold register. A power saving mode of the hardware memory segment is modified based on performing the response action. | 06-23-2011 |
20130111303 | SINGLE ERROR CORRECTION & DEVICE FAILURE DETECTION FOR X8 SDRAM DEVICES IN BL8 MEMORY OPERATION | 05-02-2013 |
20130238874 | SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER - Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L | 09-12-2013 |
20140032844 | SYSTEMS AND METHODS FOR FLUSHING A CACHE WITH MODIFIED DATA - Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache. | 01-30-2014 |
20140032845 | SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE - A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory. | 01-30-2014 |
20140032846 | SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD AND STORE ACCESSES OF A CACHE - Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data. | 01-30-2014 |
20140032856 | SYSTEMS AND METHODS FOR MAINTAINING THE COHERENCY OF A STORE COALESCING CACHE AND A LOAD CACHE - A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache. | 01-30-2014 |
20140108729 | SYSTEMS AND METHODS FOR LOAD CANCELING IN A PROCESSOR THAT IS CONNECTED TO AN EXTERNAL INTERCONNECT FABRIC - Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load canceling in a processor that is connected to an external bus, and responsive to a flush request and a corresponding cancellation of pending speculative loads from a load queue, a type of one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor, is converted from load to prefetch. Data corresponding to one or more of the pending speculative loads that are positioned in the instruction pipeline external to the processor is accessed and returned to cache as prefetch data. The prefetch data is retired in a cache location of the processor. | 04-17-2014 |
20140108730 | SYSTEMS AND METHODS FOR NON-BLOCKING IMPLEMENTATION OF CACHE FLUSH INSTRUCTIONS - Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged. | 04-17-2014 |
20140108739 | SYSTEMS AND METHODS FOR IMPLEMENTING WEAK STREAM SOFTEARE DATA AND INSTRUCTION PREFETCHING USING A HARDWARE DATA PREFETCHER - A method for weak stream software data and instruction prefetching using a hardware data prefetcher is disclosed. A method includes, determining if software includes software prefetch instructions, using a hardware data prefetcher, and, accessing the software prefetch instructions if the software includes software prefetch instructions. Using the hardware data prefetcher, weak stream software data and instruction prefetching operations are executed based on the software prefetch instructions, free of training operations. | 04-17-2014 |
20140156947 | METHOD AND APPARATUS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE TO MAINTAIN THROUGHPUT - A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block. | 06-05-2014 |
20140281242 | METHODS, SYSTEMS AND APPARATUS FOR PREDICTING THE WAY OF A SET ASSOCIATIVE CACHE - A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle. | 09-18-2014 |
20150052303 | SYSTEMS AND METHODS FOR ACQUIRING DATA FOR LOADS AT DIFFERENT ACCESS TIMES FROM HIERARCHICAL SOURCES USING A LOAD QUEUE AS A TEMPORARY STORAGE BUFFER AND COMPLETING THE LOAD EARLY - A method for acquiring cache line data associated with a load from respective hierarchical cache data storage components. As a part of the method, a store queue is accessed for one or more portions of a cache line associated with a load, and, if the one or more portions of the cache line is held in the store queue, the one or more portions of the cache line is stored in a load queue location associated with the load. The load is completed if the one or more portions of the cache line stored in the load queue location includes all portions of the cache line associated with the load. | 02-19-2015 |
20150052304 | SYSTEMS AND METHODS FOR READ REQUEST BYPASSING A LAST LEVEL CACHE THAT INTERFACES WITH AN EXTERNAL FABRIC - Methods for read request bypassing a last level cache which interfaces with an external fabric are disclosed. A method includes identifying a read request for a read transaction, generating a phantom read transaction identifier for the read transaction and forwarding the read transaction with the phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to the read transaction. The phantom read transaction identifier acts as a pointer to a real read transaction identifier. | 02-19-2015 |
20150052401 | SYSTEMS AND METHODS FOR INVASIVE DEBUG OF A PROCESSOR WITHOUT PROCESSOR EXECUTION OF INSTRUCTIONS - Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor is accessed using a debug bus and an operation is initiated that causes a debug port to gain access to registers of the processor using the memory mapped I/O. The invasive debug of the processor is executed from the debug port via registers of the processor. | 02-19-2015 |
20150067230 | SYSTEMS AND METHODS FOR FASTER READ AFTER WRITE FORWARDING USING A VIRTUAL ADDRESS - Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible. | 03-05-2015 |
20150286576 | CACHE REPLACEMENT POLICY - Cache replacement policy. In accordance with a first embodiment of the present invention, an apparatus comprises a queue memory structure configured to queue cache requests that miss a second cache after missing a first cache. The apparatus comprises additional memory associated with the queue memory structure is configured to record an evict way of the cache requests for the cache. The apparatus may be further configured to lock the evict way recorded in the additional memory, for example, to prevent reuse of the evict way. The apparatus may be further configured to unlock the evict way responsive to a fill from the second cache to the cache. The additional memory may be a component of a higher level cache. | 10-08-2015 |
20150301954 | SYSTEMS AND METHODS FOR ACCESSING A UNIFIED TRANSLATION LOOKASIDE BUFFER - Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one translation lookaside buffer (L1TLB) miss corresponding to a request for a virtual address to physical address translation, searching a cache that includes virtual addresses and page sizes that correspond to translation table entries (TTEs) that have been evicted from the L1TLB, where a page size is identified, and searching a second level TLB and identifying a physical address that is contained in the second level TLB. Access is provided to the identified physical address. | 10-22-2015 |
20150324213 | METHOD AND APPARATUS FOR PROVIDING HARDWARE SUPPORT FOR SELF-MODIFYING CODE - A method and apparatus for providing support for self modifying guest code. The apparatus includes a memory, a hardware buffer, and a processor. The processor is configured to convert guest code to native code and store converted native code equivalent of the guest code into a code cache portion of the processor. The processor is further configured to maintain the hardware buffer configured for tracking respective locations of converted code in a code cache. The hardware buffer is updated based a respective access to a respective location in the memory associated with a respective location of converted code in the code cache. The processor is further configured to perform a request to modify a memory location after accessing the hardware buffer. | 11-12-2015 |
20150339238 | SYSTEMS AND METHODS FOR FASTER READ AFTER WRITE FORWARDING USING A VIRTUAL ADDRESS - Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible. | 11-26-2015 |
20160041908 | SYSTEMS AND METHODS FOR MAINTAINING THE COHERENCY OF A STORE COALESCING CACHE AND A LOAD CACHE - A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an entry from a level one store coalescing cache to a level two cache, the entry is written into the level two cache and into the level one load cache. The writing of the entry into the level two cache and into the level one load cache is executed at the speed of access of the level two cache. | 02-11-2016 |
20160041913 | SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD AND STORE ACCESSES OF A CACHE - Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data. | 02-11-2016 |
20160041930 | SYSTEMS AND METHODS FOR SUPPORTING A PLURALITY OF LOAD ACCESSES OF A CACHE IN A SINGLE CYCLE - A method for supporting a plurality of load accesses is disclosed. A plurality of requests to access a data cache is accessed, and in response, a tag memory is accessed that maintains a plurality of copies of tags for each entry in the data cache. Tags are identified that correspond to individual requests. The data cache is accessed based on the tags that correspond to the individual requests. A plurality of requests to access the same block of the plurality of blocks causes an access arbitration that is executed in the same clock cycle as is the access of the tag memory. | 02-11-2016 |
Karthikeyan Bhargavan, Cambridge GB
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20080288622 | Managing Server Farms - Manual management of server farms is expensive. Low-level tools and the sheer complexity of the task make it prone to human error. By providing a typed interface using service combinators for managing server farms it is possible to improve automated server farm management. Metadata about a server farm is obtained, for example, from disk images, and this is used to generate a typed environment interface for accessing server farm resources. Scripts are received, from a human operator or automated process, which use the environment interface and optionally also pre-specified service combinators. The scripts are executed to assemble and link together services in the server farm to form and manage a running server farm application. By using typechecking server farm construction errors can be caught before implementation. | 11-20-2008 |
Karthikeyan Gnanamani, Chennai IN
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20130103581 | SYSTEMS AND METHODS FOR SINGLE NUMBER PAN VIRTUAL/PHYSICAL CARD - A credit/debit card that can be utilized as a virtual card or as a physical card. The system provides a single PAN (Primary Account Number) for both the virtual and the physical card so that they represent a single account. The customer can elect one of the card formats. When one format is selected, the other format is inactive. In one embodiment, the customer can toggle back and forth between formats. To distinguish between the types of card, each card has modulated non-PAN data. For example, the expiration date on each card may be modified so that uses of the card will be recognized as coming from one format or the other. | 04-25-2013 |
Karthikeyan Govindhasamy, San Diego, CA US
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20120176736 | Method and Apparatus for a Hinge - In accordance with an example embodiment of the present invention, an apparatus comprises a flexible hinge comprising first and second layers; the first layer comprising an elastomer and the second layer comprising a composite fabric. | 07-12-2012 |
Karthikeyan Jambulingam, Chennai IN
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20160087929 | METHODS AND APPARATUS FOR DOCUMENT CREATION VIA EMAIL - A system and method for creating a document in a messaging environment is described. A communication including a document specification including zero or more formatting commands and content is received from a sender and processed. The system and method determine whether the document specification is in a done condition, and iterates until done. A formatted document is also created and returned to the sender and recipients. | 03-24-2016 |
Karthikeyan Kaliappan, Middlesex GB
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20140181793 | METHOD OF AUTOMATICALLY TESTING DIFFERENT SOFTWARE APPLICATIONS FOR DEFECTS - A method of automatically testing different software applications for defects, comprising the step of a test automation enabler (a) converting recorded test scripts into a generic format that is not application-centric and (b) storing the resultant non-application centric data in generic data containers. A computer-based implementation called OPUS can be easily operated by any user with basic knowledge of software testing principles and FTAT. After minimal training the user can use OPUS to implement test automation. OPUS is process based, methodical, stable, measurable, and repeatable by following a multi-stage process which is not domain, platform or application centric. The manual process of recording the test scripts is done in a functional test automation tool (FTAT). OPUS takes the recorded scripts, converts them into non application centric data and uses them for the automated testing process. | 06-26-2014 |
Karthikeyan Kaliyamoorthi, Bangalore IN
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20080260222 | Lesion Quantification and Tracking Using Multiple Modalities - A method for lesion detection includes acquiring pre-therapy medical image data from a first modality. Post-therapy medical image data is acquired from a second modality. A transformation matrix for transforming from an image space of the first modality to an image space of the second modality is calculated. A volume of interest is defined from the medical image data of the first modality. The volume of interest includes one or more lesions. The volume of interest is automatically copied to the medical image data of the second modality using the calculated transformation matrix. Treatment is directed to the lesion using the medical image data of the second modality including the copied volume of interest data. | 10-23-2008 |
Karthikeyan Kandavelou, Pondicherry, IN US
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20130130350 | OBLIGATE HETERODIMER VARIANTS OF FOKI CLEAVAGE DOMAIN - Disclosed are methods of making and using engineered FokI cleavage domain variants. Also disclosed are methods, compositions and fusion proteins containing obligate heterodimers of engineered FokI cleavage domain variants and DNA binding domains, such as zinc finger protein (ZFP) domains and transcription activator-like effector (TALE) domains. | 05-23-2013 |
Karthikeyan Kandavelou, Puducherry IN
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20140127814 | GENERATION AND USE OF PLURIPOTENT STEM CELLS - ABSTRACT Methods, compositions, constructs, vectors, cell lines, and kits, for generating induced pluripotent stem cells by site-specific integration of pluripotency coding sequences with endonucleases for use in gene therapy, regenerative medicine, cell therapy or drug screening. | 05-08-2014 |
Karthikeyan Kaniyur-Subbian, Sathyamangalam IN
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20140288943 | HEALTHCARE RECALL MANAGEMENT - Various technologies related to managing a medical device recall are implemented. Automated recall functions can facilitate an efficient and effective recall process. Full lifecycle of the recall process can be managed including communication with patients and replacement of devices, as well as auditing and regulatory compliance. Via the technologies described herein, healthcare providers can manage a successful medical device recall. Unique device identification, electronic health records, electronic medical records, and nationwide health information networks can be supported. A unique device identifier-centric approach can support a very high degree of automation and avoid errors during any of a variety of segments in the medical device recall life cycle. | 09-25-2014 |
20140288966 | MEDICAL DEVICE SAFETY MANAGEMENT - A computer-implemented method of managing medical device safety comprises communicatively coupling a recall portal hosted on a network server to a health network and a computer database of medical records. Further, initiating a medical device recall through the recall portal and the health network. A consumer contact information associated with a medical device to be recalled is queried. A medical recall information is sent to the consumer contact information accessed from the computer database of medical records. | 09-25-2014 |
Karthikeyan Karthikeyan Venkatanarayanan, Hyderabad IN
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20110152511 | GENETICALLY TRANSFORMED MICROORGANISMS WITH SIMULTANEOUS ENHANCEMENT OF REDUCTION POTENTIAL AND REDUCTIVE ENZYME ACTIVITIES FOR BIOMASS FERMENTATION - The present invention describes the genetic engineering of production microorganisms used in biotechnology to improve their properties so that they produce industrially useful products more efficiently from fermentable sugars derived from biomass. The engineered microorganisms endowed with functional coupling of oxidation and reduction of substrates by dehydrogenases requiring pyridine nucleotides (NAD/NADH) result in simultaneous enhancement of reduction potential enzyme activity involving the transfer of electrons. In particular, this invention relates to the construction of an excisable gene expression cassette for expression of two different dehydrogenases leading to enhanced production of ethanol. | 06-23-2011 |
Karthikeyan Kasthuriswamy, K.r. Puram IN
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20100281072 | AUTOMATED MIGRATION OF TRANSLATION MAPS FOR USE IN EXCHANGING DOCUMENTS BETWEEN ENTITIES - A method for migrating a legacy translation map to an evolved translation map includes determining an input file structure from input file structure information in the legacy translation map, determining an output file structure from output file structure information in the legacy translation map, and creating an XML binding object representation of source code for the input and output file structure. The method may further include creating an evolved language object representation of translation instructions in the legacy translation map, adding temporary segments to the XML binding object representation for the input file structure, and generating evolved language object representation of instructions to write input data into the temporary segments. The evolved language object representation of translation instructions is then merged into the XML binding object representation. The evolved translation map is then generated as an XML file based on the XML binding object representation resulting from the merging. | 11-04-2010 |
Karthikeyan Kumaresan, Tucson, AZ US
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20100239914 | CATHODE FOR LITHIUM BATTERY - The present invention relates to cathodes used in electrochemical cells. A force, or forces, applied to portions of an electrochemical cell as described in this application can reduce irregularity or roughening of an electrode surface of the cell, improving performance. The cathodes described herein may possess enhanced properties that render them particularly suitable for use in electrochemical cells designed to be charged and/or discharged while a force is applied. In some embodiments, the cathode retains sufficient porosity to charge and discharge effectively when a force is applied to the cell. Cathodes described herein may also comprise relatively high electrolyte-accessible conductive material (e.g., carbon) areas. The cathode may comprise a relatively low ratio of the amount of binder and/or mass of electrolyte to cathode active material (e.g., sulfur) ratio in some instances. In some embodiments, electrochemical cells comprising the cathodes described herein may achieve relatively high specific capacities and/or relatively high discharge current densities. In addition, the cathode described herein may exhibit relatively high cathode active material (e.g., sulfur) utilization during charge and discharge. In still further cases, the electrical conductivity between conductive material in the cathode (e.g., carbon) may be enhanced during the application of the force. | 09-23-2010 |
20120070746 | LOW ELECTROLYTE ELECTROCHEMICAL CELLS - Electrochemical cells including components and configurations for electrochemical cells, such as rechargeable lithium batteries, are provided. The electrochemical cells described herein may include a combination of components arranged in certain configurations that work together to increase performance of the electrochemical cell. In some embodiments, such combinations of components and configurations described herein may minimize defects, inefficiencies, or other drawbacks that might otherwise exist inherently in prior electrochemical cells, or that might exist inherently in prior electrochemical cells using the same or similar materials as those described herein, but arranged differently. | 03-22-2012 |
20140193713 | PASSIVATION OF ELECTRODES IN ELECTROCHEMICAL CELLS - Electrochemical cells having desirable electronic and ionic conductivities, and associated systems and methods, are generally described. | 07-10-2014 |
20140193723 | CONDUCTIVITY CONTROL IN ELECTROCHEMICAL CELLS - Electrochemical cells having desirable electronic and ionic conductivities, and associated systems and methods, are generally described. | 07-10-2014 |
Karthikeyan Lakshmi Narayanan, Tamil Nadu IN
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20120035357 | PROCESS FOR THE PREPARATION OF CARBAPENEM ANTIBIOTIC - The present invention relates to an improved process for the preparation of the carbapenem antibiotic of formula (I) or its salts, hydrates and esters. The present invention further provides novel crystalline form of compound of general formula (III), wherein R | 02-09-2012 |
Karthikeyan Maharajapuram S., Burscheid DE
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20080315654 | Vehicle Seat - A vehicle seat ( | 12-25-2008 |
Karthikeyan Muthalagu, Morrisville, NC US
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20150339426 | NEGATIVE PLANE USAGE WITH A VIRTUAL HIERARCHICAL LAYER - A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification. | 11-26-2015 |
20150339433 | VIRTUAL CELL MODEL USAGE - Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created. | 11-26-2015 |
20150339434 | VIRTUAL HIERARCHICAL LAYER PROPAGATION - Simulation and verification are critical to analyzing a semiconductor design using design rule checking (DRC) to verify design rules for manufacturing (DRM). The efficient use of computational resources including runtimes and resource requirements is a key component of the analysis. A virtual hierarchical layer (VHL) with shapes is generated for the design analysis of a design, including cells and hierarchical design levels. A cell and multiple instances of the cell are identified in the design. A VHL based on polygons overlapping the cell is generated in response to an algorithmic operation. The VHL shapes are propagated to subsequent algorithmic operations. The algorithmic operations update the VHL shapes. Shapes are filtered out of the VHL shapes as part of the updating. The VHL shapes are propagated through a chain of operations. | 11-26-2015 |
Karthikeyan Narasingapuram Arumugam, Vellore IN
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20160031855 | PROTEIN KINASE INHIBITORS - A compound of formula (I) | 02-04-2016 |
Karthikeyan Nenmeli Ravichandran, Bellevue, WA US
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20140376560 | LOGICAL SWITCH - Configuring third party solutions to operate with virtual machines and virtual switches in a distributed network environment. The method includes receiving information at a logical switch about third party solutions in a distributed network. The method further includes receiving information at the logical switch about requirements for virtual components of the distributed network. The method further includes the logical switch automatically configuring third party solutions in the distributed network to meet the requirements for the virtual components of the distributed network. | 12-25-2014 |
Karthikeyan Paramanandam, Bangalore IN
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20130148463 | PROCESS AND APPARATUS FOR MIXING TWO STREAMS OF CATALYST - A process and apparatus for mixing streams of regenerated and carbonized catalyst involves passing a catalyst stream into and out of a chamber in a lower section of a riser. The chamber fosters mixing of the catalyst streams to reduce their temperature differential before contacting hydrocarbon feed. | 06-13-2013 |
20130148464 | PROCESS AND APPARATUS FOR MIXING TWO STREAMS OF CATALYST - A process and apparatus for mixing streams of regenerated and carbonized catalyst involves passing a catalyst stream into and out of a chamber in a lower section of a riser. The chamber fosters mixing of the catalyst streams to reduce their temperature differential before contacting hydrocarbon feed. | 06-13-2013 |
20130148465 | PROCESS AND APPARATUS FOR MIXING TWO STREAMS OF CATALYST - A process and apparatus for mixing streams of regenerated and carbonized catalyst involves passing a catalyst stream into and out of a chamber in a lower section of a riser. The chamber fosters mixing of the catalyst streams to reduce their temperature differential before contacting hydrocarbon feed. | 06-13-2013 |
20130150233 | PROCESS AND APPARATUS FOR MIXING TWO STREAMS OF CATALYST - A process and apparatus for mixing streams of regenerated and carbonized catalyst involves passing a catalyst stream into and out of a chamber in a lower section of a riser. The chamber fosters mixing of the catalyst streams to reduce their temperature differential before contacting hydrocarbon feed. | 06-13-2013 |
Karthikeyan Pichaikannu, Orange, CA US
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20090293250 | Compact universal offset pulling head for fasteners - A universal offset pulling head assembly for exerting an axial pulling force on a fastener allows the same pulling head assembly to be utilized for a variety of different fastener sizes and types by exchanging a front plate assembly, where the front plate assembly may comprise variable nose pieces according to the type of fastener to be installed. Because the front plate assembly is subject to the most severe wear, other components of the pulling head assembly may continue to be utilized and the front plate assembly discarded. The disclosed pulling head assembly utilizes a stationary guiding member which prevents damage which might otherwise occur because of severe bending moments. | 12-03-2009 |
Karthikeyan Ponnalagu, Madurai IN
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20090099855 | Method for Generating Software Variants - A method generates, based on an original business process comprising at least one component, a variant business process comprising at least one variation compared to the original business process. The method comprises the steps of developing a variant meta-model, representing the at least one variation, instantiating and verifying the developed variant meta-model portion to obtain a variant model, and implementing the variant model to generate the variant. The method also comprises developing a formalism for defining the at least one variation. | 04-16-2009 |
20090109225 | SYSTEM AND METHOD TO ORGANIZE ASSETS IN A REPOSITORY - The embodiments of the invention provide a method of organizing assets having artifacts in a repository. The method begins by organizing artifacts of at least one of the assets as internal nodes in a graph based on a context. The method simultaneously organizes the assets as external nodes in the graph based on the context. The internal nodes comprise artifacts having metadata that is updated by an artifact producer and/or an asset producer. Moreover, the external nodes comprise artifacts that are defined and/or updated by roles other than an artifact producer and/or an asset producer. | 04-30-2009 |
20100305986 | Using Service Exposure Criteria - Techniques for performing service exposure for reuse of one or more services are provided. The techniques include analyzing applicability of service criteria for a candidate service, identifying one or more services that are contextually-related to the candidate service, and using the service criteria applicable to the candidate service to expose the one or more services contextually-related to the candidate service. | 12-02-2010 |
20130138798 | PREDICTIVE AND DYNAMIC RESOURCE PROVISIONING WITH TENANCY MATCHING OF HEALTH METRICS IN CLOUD SYSTEMS - According to one embodiment of the present invention, a method computing resources are dynamically provisioned to meet service level objectives in a cloud computing environment. Resources available for provisioning to the cloud computing environment are determined and the quality thereof monitored. Current resource needs for a cloud job tenancy are determined, and selected resources are dynamically provisioned from resources available for provisioning based on the current resource needs and the quality of the resources available in order to meet the cloud job tenancy and the service level objectives. | 05-30-2013 |
20130138806 | PREDICTIVE AND DYNAMIC RESOURCE PROVISIONING WITH TENANCY MATCHING OF HEALTH METRICS IN CLOUD SYSTEMS - According to one embodiment of the present invention, a method computing resources are dynamically provisioned to meet service level objectives in a cloud computing environment. Resources available for provisioning to the cloud computing environment are determined and the quality thereof monitored. Current resource needs for a cloud job tenancy are determined, and selected resources are dynamically provisioned from resources available for provisioning based on the current resource needs and the quality of the resources available in order to meet the cloud job tenancy and the service level objectives. | 05-30-2013 |
Karthikeyan Ponnalagu, Tamil Nadu IN
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20120072227 | AUTOMATICALLY GENERATING HIGH QUALITY SOA DESIGN FROM BUSINESS PROCESS MAPS BASED ON SPECIFIED QUALITY GOALS - Methods and systems for automatically generating a service oriented architecture (SOA) design. A set of business process maps for the domain under consideration is defined and a design quality goal (function) that should be met (optimized) is specified. The design goal/function involves SOA metrics like coupling, cohesion, granularity, etc., which the system under consideration is pre-programmed to compute on any SOA design. The system takes as input the set of business process maps and the design quality goal/functions. It first generates semantic business process maps by identifying key concepts that occur in the task and business item descriptions. Next, it efficiently searches the service design space by starting with a seed design and employing a sequence of moves to iteratively optimize it. It outputs a set of possible SOA designs that meet the specified quality goals or optimizes the specified function, from where a user may select the final design. | 03-22-2012 |
20120123986 | SYSTEMS AND METHODS FOR MODELING AND ANALYZING SOLUTION REQUIREMENTS AND ASSETS - Systems and associated methods for capturing and storing asset analysis details are described. Systems and methods provide for building a model of the particular asset requirement for a specific purpose and a model of the range of capabilities that a particular asset can provide. The mapping of these two models allows for the identification of the best asset for a particular solution requirement. An asset match may occur when an asset capability model whose functional and non-functional capabilities subsume the functional and non-functional requirements specified in the asset requirements model. | 05-17-2012 |
20130061203 | Modeling Task-Site Allocation Networks - A method, an apparatus and an article of manufacture for modeling a task-site allocation. The method includes generating a task-site allocation network based on at least one site-task pair and at least one site-centric constraint of at least two sites, wherein generating a task-site allocation network comprises generating a task-specific constraints model based on task context information and generating a task-site pair that satisfies at least one constraint based on the task-specific constraints model, and determining a preferred allocation of task to site by comparing estimated task-site allocation cost between a single site allocation and a distributed site allocation among the at least two sites. | 03-07-2013 |
Karthikeyan Ponnalagu, Nadu IN
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20120278267 | METHODS AND ARRANGEMENTS FOR DYNAMICALLY GENERATING ESTIMATION TRENDLINES - Methods and arrangements for dynamic trendline generation. Input data are assimilated at a capture timepoint from an estimation tool. The input data are filtered, and an estimation-centric map is created from the filtered data ; this creating of a map includes generating an estimation data tree. A trendline is dynamically generated responsive to a request, wherein this generating of a trendline includes applying the estimation data tree to the input data. The dynamically generated trendline is supplied to the estimation tool. | 11-01-2012 |
20130290500 | DIFFERENTIATED SERVICE IDENTIFICATION IN A NETWORKED COMPUTING ENVIRONMENT - Embodiments of the present invention provide an approach for differentiated service identification/exposure in a networked computing environment (e.g., a cloud computing environment). In a typical embodiment, input model criteria will be generated. Such criteria may (among other things): identify service categories based on contextual bindings and domain centric functions; identify inter-service dependencies for a given business model (BPM); and/or provide dynamic validation of services to be exposed/identified. Embodiments of the present invention may further analyze service exposure criteria to provide efficient and accurate service exposure decisions as well as validation of the service exposure. This approach allows for consistent service exposure determinations based on decision histories of similarly (2-dimensional) aligned services in the past. This approach further allows for a validation assessment that is based on actual metrics of service usage verses an estimated usage at the time of service implementation. | 10-31-2013 |
Karthikeyan Ramamurthi, Bangalore IN
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20100005373 | Majority Voting Logic Circuit for Dual Bus Width - A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width. | 01-07-2010 |
Karthikeyan Sabapathi, Hyderabad IN
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20150078334 | APPARATUS AND METHODS OF EFFICIENT SIB READING DURING WCDMA ACQUISITION IN MULTI-SIM MODEMS - Methods and apparatus are described for a method of cell acquisition, comprising obtaining, during an idle mode, a primary scrambling code (PSC) of a first cell of a first radio access technology (RAT) by a user equipment having a first subscription to the first RAT and a second subscription to a second RAT. Further, the methods and apparatus include performing a system information block (SIB) reading procedure for the first cell for one or more SIBs. Additionally, the methods and apparatus include determining whether any of the one or more SIBs are successfully decoded within a first time threshold during the SIB reading procedure for the first cell. Moreover, the methods and apparatus include aborting the SIB reading procedure for the first cell when the one or more SIBs are not successfully decoded within the first time threshold. | 03-19-2015 |
20150296364 | System and Methods for Increasing Efficiency of a Public Land Mobile Network Search in Service Acquisition on a Multi-SIM Wireless Device - Methods and devices are disclosed for enabling improved service acquisition on a first SIM of a multi-SIM wireless communication device. After the first SIM has lost service, the wireless device may detect a condition triggering a public mobile land network (PLMN) selection associated with the first SIM, receive an indication that service acquisition settings of the first SIM are set to a manual mode, and determine whether the second SIM is in idle mode. Upon determining that the second SIM is in idle mode, the wireless device may identify timing of a sleep cycle implemented by the second SIM, and perform the PLMN search using the first and second radio resources. | 10-15-2015 |
20150382361 | Handling Transmit Blanking in Multi-Carrier High-Speed Uplink Packet Access-Capable Multi-SIM-Multi-Active Modems - Various embodiments implemented on a mobile communication device (e.g., a multi-carrier-capable communication device) mitigate the degraded performance experienced by an aggressor subscription performing transmit blanking on an interfering carrier frequency during a coexistence event by leveraging the availability of a non-interfering carrier frequency. In various embodiments, the mobile communication device may signal the aggressor subscription's network to adjust resources granted to the interfering carrier frequency and the non-interfering carrier frequency to improve overall data throughput and/or to reduce the likelihood of reception problems, such as increased retransmission requests from the network and stalls/delays in sending subsequent transport blocks. If no change in resources is signaled by the network, the mobile communication device may reduce a size of transport blocks transmitted on the interfering carrier frequency. The mobile communication device may signal the network to return to normal resource allocations or transmit normal size transport blocks when the coexistence event ends. | 12-31-2015 |
Karthikeyan Sabhanatarajan, San Francisco, CA US
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20140044126 | Scalable Media Access Control Protocol Synchronization Techniques for Fabric Extender Based Emulated Switch Deployments - Techniques are provided to prevent switches in a data center fabric path environment with fabric path extension devices from media access control (MAC) address flooding and MAC address table overflow. In such an environment, endpoints associated with virtual port channels are connected to multiple switches which normally would perform MAC address flooding across all switch forwarding engines. The switches in the fabric path exchange MAC synchronization messages based on source/destination specific connectivity such that MAC broadcast messages that advertise source/destination MAC addresses for endpoints do not have to be repeatedly sent and their corresponding MAC lookup tables do not have to be updated or include unnecessary MAC table entries. | 02-13-2014 |
Karthikeyan Sadhasivam, Richardson, TX US
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20090217039 | System, Method and Apparatus for Authenticating Calls - The present invention provides a system, method and apparatus for authenticating calls that is a robust Anti-vishing solution. The present invention can identify Caller ID spoofing, verify dialed number to detect man-in-the middle and verify called party against dialed digits to detect impersonation. This solution can handle calls coming from any phone any where with little impact on user experience. Two separate solutions are tailored for smart phones (communication devices capable of running application software) and traditional phones to reduce the impact to user experience while providing robust verification. | 08-27-2009 |
20150124945 | SYSTEM, METHOD AND APPARATUS FOR AUTHENTICATING CALLS - The present invention provides a system, method and apparatus for authenticating calls that is a robust Anti-vishing solution. The present invention can identify Caller ID spoofing, verify dialed number to detect man-in-the middle and verify called party against dialed digits to detect impersonation. This solution can handle calls coming from any phone any where with little impact on user experience. Two separate solutions are tailored for smart phones (communication devices capable of running application software) and traditional phones to reduce the impact to user experience while providing robust verification. | 05-07-2015 |
Karthikeyan Sankaralingam, Madison, WI US
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20100238942 | LOOKUP ENGINE WITH PROGRAMMABLE MEMORY TOPOLOGY - An architecture for a specialized electronic computer for high-speed data lookup employs a set of tiles each with independent processors and lookup memory portions. The tiles may be programmed to interconnect to form different memory topologies optimized for the particular task. | 09-23-2010 |
20120284562 | Computer Processor Providing Error Recovery with Idempotent Regions - A computer architecture allows for simplified recovery after mis-speculation during speculative execution by controlling speculation to occur within idempotent regions that may be recovered by re-execution of the region without the need for restoring complex state information from checkpoints. A compiler for increasing the size of idempotent regions is also disclosed. | 11-08-2012 |
20140019735 | Computer Processor Providing Exception Handling with Reduced State Storage - A computer architecture allows for simplified exception handling by restarting the program after exceptions at the beginning of idempotent regions, the idempotent regions allowing re-execution without the need for restoring complex state information from checkpoints. Recovery from mis-speculation may be provided by a similar mechanism but using smaller idempotent regions reflecting a more frequent occurrence of mis-speculation. A compiler generating different idempotent regions for speculation and exception handling is also disclosed. | 01-16-2014 |
20140044135 | Lookup Engine with Reconfigurable Low Latency Computational Tiles - An architecture for a specialized electronic computer for high-speed data lookup employs a set of tiles each with independent logic elements lookup memory portions. The tiles may each comprise gate-array-like functional units that may be wired together by a multi-way switch for extremely low latency. | 02-13-2014 |
20150061707 | INTEGRATED CIRCUIT PROVIDING FAULT PREDICTION - The prediction of hardware failure is obtained by operating two redundant circuit modules while one circuit module is artificially aged. The output of the two circuit modules is compared and a discrepancy between outputs indicates a projected failure of the aged modules. Aging may be accomplished by one or a combination of lowering operating voltages and re-phasing a sampling clock to reduce slack time both of which provide increased sensitivity to gate delay. | 03-05-2015 |
20150261528 | COMPUTER ACCELERATOR SYSTEM WITH IMPROVED EFFICIENCY - A specialized memory access processor is placed between a main processor and accelerator hardware to handle memory access for the accelerator hardware. The architecture of the memory access processor is designed to allow lower energy memory accesses than can be obtained by the main processor in providing data to the hardware accelerator while providing the hardware accelerator with a sufficiently high bandwidth memory channel. In some embodiments, the main processor may enter a sleep state during accelerator calculations to substantially lower energy consumption. | 09-17-2015 |
20150261536 | METHOD OF ESTIMATING PROGRAM SPEED-UP WITH HIGHLY PARALLEL ARCHITECTURES - The amount of speed-up that can be obtained by moving a program to a parallel architecture is determined by a model associating speed-up to micro-architecture independent features of the program execution. The model may be generated, for example, by linear regression, by evaluating programs that have been ported to parallel architectures where the micro-architecture independent features are known. | 09-17-2015 |
20160041856 | Memory Processing Core Architecture - Aspects of the present invention provide a memory system comprising a plurality of stacked memory layers, each memory layer divided into memory sections, wherein each memory section connects to a neighboring memory section in an adjacent memory layer, and a logic layer stacked among the plurality of memory layers, the logic layer divided into logic sections, each logic section including a memory processing core, wherein each logic section connects to a neighboring memory section in an adjacent memory layer to form a memory vault of connected logic and memory sections, and wherein each logic section is configured to communicate directly or indirectly with a host processor. Accordingly, each memory processing core may be configured to respond to a procedure call from the host processor by processing data stored in its respective memory vault and providing a result to the host processor. As a result, increased performance may be provided. | 02-11-2016 |
Karthikeyan Sathrugnan, Singapore SG
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20110163032 | HIGH RECOVERY SULFATE REMOVAL PROCESS - A high recovery sulfate removal process comprises treating a feed water stream conditioned with antiscalant from a source with a reverse osmosis membrane system to produce a purified water permeate stream and a reject stream containing the retained or rejected ions and organic matter. The reject stream is further treated to remove dissolved and suspended species. The reject stream flows to a desaturation/clarification process. A preferred process includes a constant stirred tank reactor (CSTR) where co-precipitation agent is added followed by a clarifier. Water recycled from the clarifier overflow is blended with feed water stream. The removed solids are collected as sludge or a slurry and disposed of in a manner consistent with applicable regulations. | 07-07-2011 |
20110233153 | RADIAL FLOW COLUMN - Aspects and embodiments of the present invention are directed to apparatus and methods of filtering a fluid to reduce a level of at least one contaminant therein. The filtering of the fluid may be accomplished with a radial flow filtration column comprising a fluid chamber having an inlet, an outlet, and a side wall, an inner permeable retainer positioned in the fluid chamber, an outer permeable retainer positioned in the fluid chamber spaced apart from and surrounding the inner permeable retainer, a media bed compartment formed between the inner permeable retainer and the outer permeable retainer, and an adjustable element biased into the media bed compartment and configured to maintain a predetermined packing density of a media bed to be disposed within the media bed compartment. | 09-29-2011 |
20120205313 | Sulfate removal from aqueous waste streams with recycle - This invention provides for sulfate removal from a water source by a reverse osmosis (RO) or nanofiltration (NF) process where the concentrate stream is treated to precipitate and remove reject sulfate and recycle the discharged concentrate water and any backwash water used to clean a filter used to prepare feed water for the RO or NF process. | 08-16-2012 |
20130334134 | INTEGRATED SELENIUM REMOVAL SYSTEM FOR WASTE WATER - The inventive process scheme and its various embodiments described herein will comprise filtering a selenium containing water by reverse osmosis or nanofiltration to produce a primary permeate stream at least meeting the water stream effluent discharge requirements of the location and a concentrate stream containing the removed selenium and other species, a RO or NF concentrate treatment specific to the case which will treat and reduce the selenium content of the concentrate, optionally in conjunction with a sulfate removal process, and result in a highly concentrated sludge or other output, and a selenium depleted aqueous overflow stream, a portion of which will be combined with the primary permeate stream so that the selenium content of the combined stream does not exceed the local requirement, and the reminder of the selenium depleted aqueous overflow stream will be returned to be combined with the selenium containing water entering the inlet of the primary reverse osmosis treatment. | 12-19-2013 |
Karthikeyan Selvarajan, Thornleigh AU
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20130008439 | ELBOW ASSEMBLY - An elbow assembly for a mask system includes an elbow including a slot and a port, an anti-asphyxia valve adapted to be received within the slot and including a flap portion adapted to selectively close the port depending on the presence of pressurized gas, and a clip member to secure the anti-asphyxia valve to the elbow. The clip member includes a slot that is adapted to interlock with a protrusion provided to the anti-asphyxia valve. | 01-10-2013 |
20130112203 | BLADDER CUSHION, FOREHEAD CUSHION, HEADGEAR STRAPS, HEADGEAR CAP AND/OR CHINSTRAP - A cushion for a patient interface includes two or more bladders arranged in concentric relation. Each of the bladders includes a face-contacting portion adapted to engage the patient's face, and each of the bladders is adapted to be pressurized independently from one another. At least one of the bladders is an active bladder that is pressurized to at least a sealing pressure to form a continuous seal with the patient's face in use. | 05-09-2013 |
20130233316 | INTERCHANGEABLE MASK ASSEMBLY - A mask assembly adapted for use with a positive airway pressure device includes a mask frame, a cushion provided to the frame, a forehead support assembly, and a neck to connect the frame to the forehead support assembly. The neck includes at least one wall including a first edge and a second edge, wherein lower ends of the first edge and the second edge converge towards one another in an upward direction and upper ends of the first edge and second edge diverge from one another in an upward direction. The mask assembly is configured so that a relatively narrow portion of the neck overlies the bridge of the nose or is between the eyes of a user. The relatively narrow portion is a portion of the neck where a distance between the first edge and second edge is smallest. | 09-12-2013 |
20130306066 | ELBOW ASSEMBLY - An elbow assembly for a mask system includes an elbow including a slot and a port, an anti-asphyxia valve adapted to be received within the slot and including a flap portion adapted to selectively close the port depending on the presence of pressurized gas, and a support member to secure the anti-asphyxia valve to the elbow. The support member includes a slot that is adapted to interlock with a protrusion provided to the anti-asphyxia valve. | 11-21-2013 |
Karthikeyan Sethuramasubbu, Redmond, WA US
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20100313186 | DEVELOPER-MANAGED DEBUGGER DATA RECORDS - A developer analysis record supports debugging. One developer analysis record contains a copy of a debuggee source code expression including one or more variables. An expression location in the record specifies the location of the expression within debuggee source code, and an expression scope specifies the scope of the expression within the source code. Developer comments about the expression may be stored in the record, distinct from source code and free from programming language syntax restrictions. The developer analysis record can be stored by a developer during one debugger session and then retrieved by the same or another developer during a later debugger session. The developer analysis record can be displayed and updated in a floating window, such as a tear-off floating datatip window. | 12-09-2010 |
Karthikeyan Shanmugavadivelu, San Diego, CA US
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20130155308 | METHOD AND APPARATUS TO ENHANCE DETAILS IN AN IMAGE - Methods, apparatus, and computer readable media enhance details in a preview image for an imaging device. In one method, an image of a scene is captured with an image sensor, one or more objects of interest may be detected in the scene, a window layout for a preview window can be displayed, a composite image is generated, the composite image is displayed on a preview display. The composite image may include the captured scene along with an enhanced detail window containing the object of interest. The object of interest may be a face. The apparatus may include a touch screen display, with the position or size of the enhanced detail window changeable via gesture inputs detected on the touchscreen display. Which object of interest is displayed in the detail window may be changed from one object of interest to another through gesture inputs. | 06-20-2013 |
20130201359 | METHOD AND APPARATUS FOR UNATTENDED IMAGE CAPTURE - Described is a method and apparatus for unattended image capture that can identify subjects or faces within an image captured with an image sensor. The methods and apparatus may then score the image based, at least in part, on scores of detected subjects or faces in the image, scores of facial expressions, a focus score, exposure score, stability score, or audio score. If the score of the image is above a threshold, a snapshot image may be stored to a data store on the imaging device. If the score of the image is below a threshold, one or more audible prompts may be generated indicating that subjects should change positions, smile or remain more still during the image capture process. | 08-08-2013 |
20140028885 | METHOD AND APPARATUS FOR DUAL CAMERA SHUTTER - Described herein are methods and devices that employ a dual shutter button feature associated with an image capture device to recommend a capture mode to a user based on one or more parameters analyzed by the image capture system. As described, providing a primary shutter button and a secondary shutter button enables the user to capture in both a standard capture mode by using the primary shutter button and in an alternate mode by using a secondary shutter button. | 01-30-2014 |
20150062434 | SYSTEMS, DEVICES AND METHODS FOR DISPLAYING PICTURES IN A PICTURE - Systems, devices, and methods of displaying and/or recording multiple pictures in a picture (PIP) on the same display of a digital display device are disclosed. The PIPs can show objects from the main field view of the display device, such as a front camera lens, as well as objects from a different field of view, such as a back camera lens. The PIPs can further track the objects that are being displayed. | 03-05-2015 |
20150215528 | METHOD AND APPARATUS FOR UNATTENDED IMAGE CAPTURE - Described is a method and apparatus for unattended image capture that can identify subjects or faces within an image captured with an image sensor. The methods and apparatus may then score the image based, at least in part, on scores of detected subjects or faces in the image, scores of facial expressions, a focus score, exposure score, stability score, or audio score. If the score of the image is above a threshold, a snapshot image may be stored to a data store on the imaging device. In some aspects, if the score of the image is below a threshold, one or more audible prompts may be generated indicating that subjects should change positions, smile or remain more still during the image capture process. | 07-30-2015 |
Karthikeyan Shanmugavelu, Chennai IN
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20140176255 | Compact micro strip directional coupler with high directivity for broadband applications - The directional coupler supports ultra high bandwidth of 5600 MHz (from 400 MHz to 6 GHz) in compact structure and also provides high directivity of (>15 dB). The coupler uses a two stage micro-strip directional coupler for a frequency range of 400 MHz to 6 GHz, where the first stage supports a frequency of operation from 0.4 to 1 GHZ and the second stage supports a frequency of operation from 1 GHz to 6 GHz and the required coupled port can be chosen using a radio frequency switch as required by the application used in. | 06-26-2014 |
Karthikeyan Sharavanan, Mannheim DE
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20090275724 | IONIC LIQUIDS IN THE PREPARATION OF POMS - Process for preparing polyoxymethylenes by polymerization of the monomers a) in the presence of cationically active initiators b) and, if appropriate in the presence of regulators c) and subsequent deactivation d) and discharge from the reactor, wherein at least one ionic liquid is used as initiator b). | 11-05-2009 |
20100291389 | COATED POLYOXYMETHYLENES - Coated polyoxymethylene moldings comprising at least one polyoxymethylene homo- or copolymer A), and also, if appropriate, further additives B), which has been coated on the surface with at least one binder C) and one formaldehyde scavenger D), wherein the binder C) used comprises a polyalkylene oxide C | 11-18-2010 |
20100324184 | COATED POLYOXYMETHYLENES - The present invention relates to coated polyoxymethylene moldings comprising at least one polyoxymethylene homo- or copolymer A), and also, if appropriate, further additives B), which has been coated on the surface with at least one binder C) and one formaldehyde scavenger D), wherein the binder C) used comprises a polyalkylene oxide C | 12-23-2010 |
20110313086 | POLYOXYMETHYLENES FOR DIESEL APPLICATIONS - Thermoplastic molding materials comprising | 12-22-2011 |
Karthikeyan Sharavanan, Mannheim IN
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20100316865 | COATED POLYOXYMETHYLENES - The present invention relates to coated polyoxymethylene moldings, comprising at least one polyoxymethylene homo- or copolymer A), and also, if appropriate, further additives B), which has been coated on the surface with at least one binder C) and one formaldehyde scavenger D), wherein the binder C) used comprises a polyalkylene oxide C | 12-16-2010 |
Karthikeyan Soundarapandian, Plano, TX US
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20100073207 | Delta-Sigma Analog-to-Digital Converters and Methods to Calibrate Delta-Sigma Analog-to-Digital Converters - Delta-sigma analog-to-digital converters (ADCs) and methods to calibrate methods to delta-sigma ADCs are disclosed. In one particular example, a delta-sigma ADC is described, including an n-bit feedback digital-to-analog converter (DAC) having a number of unit elements, and is configured to provide a feedback signal to a summing device, which generates a difference signal based on an analog input signal and the feedback signal. An n-bit ADC is included to generate an n-bit digital signal based on the difference signal. A dynamic element matching device selects one or more unit elements in the DAC based on the n-bit digital signal. A storage device, such as a memory, stores error coefficients corresponding to the plurality of unit elements. Finally, a digital corrector is included to receive the selection of unit elements, receive error coefficients corresponding to the selected unit elements, and adjust the n-bit digital signal based on the received error coefficients. | 03-25-2010 |
20120169416 | CIRCUIT AND METHOD FOR REDUCING INPUT LEAKAGE IN CHOPPED AMPLIFIER DURING OVERLOAD CONDITIONS - A chopper-stabilized amplifier ( | 07-05-2012 |
20140257049 | WEARABLE HEART MONITORING APPARATUS - An apparatus mountable on a wearer's wrist includes a housing having at front portion and an opposite a back portion. The back portion is wearably positionable in contact with the wearer's wrist. The apparatus includes a PPG circuit for generating a PPG signal. The PPG circuit includes a light source and a photosensor on the housing back portion. The PPG signal may be used to continuously determine the wearer's a pulse rate. The PPG signal may also be used in combination with an ECG signal to determine the wearer's instantaneous blood pressure. The ECG signal may also be used to determine the wear's heart rate. The ECG signal may be generated with an electrode mounted on the back of the housing and another electrode mounted on another portion of the housing, such as the back or one or more of the sides. | 09-11-2014 |
Karthikeyan Subbaraj, Virudunagar IN
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20130018674 | SYSTEM AND METHOD FOR RADIOLOGY WORKFLOW MANAGEMENT AND A TOOL THEREFROMAANM Bedi; RickyAACI BangaloreAACO INAAGP Bedi; Ricky Bangalore INAANM Rao; Raghavendra RamachandraAACI BangaloreAACO INAAGP Rao; Raghavendra Ramachandra Bangalore INAANM Ravinutala; Raghavendra KumarAACI BangaloreAACO INAAGP Ravinutala; Raghavendra Kumar Bangalore INAANM Pandurangan; VijayAACI ThiruvarurAACO INAAGP Pandurangan; Vijay Thiruvarur INAANM Subbaraj; KarthikeyanAACI VirudunagarAACO INAAGP Subbaraj; Karthikeyan Virudunagar IN - A method and system for managing radiology study orders is disclosed. The method includes the steps for creating an order for a radiology study; receiving one or more images; reconciling an image from one or more images with the order, based on a reconciliation rule set to obtain the radiology study; assigning a radiologist for the radiology study based on auto-scheduling rule set and control parameters; reading of the radiology study by the radiologist; recording of a radiology report for the radiology study by the radiologist; generating a quality index for the radiologist based on the radiology report; sending the radiology report to a physician; and approving of the radiology report by the physician. | 01-17-2013 |
Karthikeyan Swamiappan, Tamilnadu IN
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20160049183 | STROBE GATING ADAPTION AND TRAINING IN A MEMORY CONTROLLER - A memory controller includes a differential receiver circuitry to receive a differential data strobe signal pair and to generate a first data strobe signal based on the differential data strobe signal pair. The differential data strobe signal pair comprises a first signal and a second signal. The memory controller also includes a single ended receiver circuitry to receive the first signal of the differential data strobe signal pair and to generate a second data strobe signal based on the first signal of the differential data strobe signal pair. The memory controller further includes circuitry to generate a gating signal for gating the first data strobe signal, the circuitry generating the gating signal based on the second data strobe signal. | 02-18-2016 |
Karthikeyan Thamilarasu, Atlanta, GA US
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20140208426 | SYSTEMS AND METHODS FOR DYNAMIC CLOUD-BASED MALWARE BEHAVIOR ANALYSIS - A cloud-based method, a behavioral analysis system, and a cloud-based security system can include a plurality of nodes communicatively coupled to one or more users, wherein the plurality of nodes each perform inline monitoring for one of the one or more users for security comprising malware detection and preclusion; and a behavioral analysis system communicatively coupled to the plurality of nodes, wherein the behavioral analysis system performs offline analysis for any suspicious content from the one or more users which is flagged by the plurality of nodes; wherein the plurality of nodes each comprise a set of known malware signatures for the inline monitoring that is periodically updated by the behavioral analysis system based on the offline analysis for the suspicious content. | 07-24-2014 |
20150319182 | SYSTEMS AND METHODS FOR DYNAMIC CLOUD-BASED MALWARE BEHAVIOR ANALYSIS - A cloud-based method, a behavioral analysis system, and a cloud-based security system can include a plurality of nodes communicatively coupled to one or more users, wherein the plurality of nodes each perform inline monitoring for one of the one or more users for security comprising malware detection and preclusion; and a behavioral analysis system communicatively coupled to the plurality of nodes, wherein the behavioral analysis system performs offline analysis for any suspicious content from the one or more users which is flagged by the plurality of nodes; wherein the plurality of nodes each comprise a set of known malware signatures for the inline monitoring that is periodically updated by the behavioral analysis system based on the offline analysis for the suspicious content. | 11-05-2015 |
Karthikeyan Vaithianathan, Little Rock, AR US
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20130027416 | GATHER METHOD AND APPARATUS FOR MEDIA PROCESSING ACCELERATORS - Apparatus, systems and methods are described including dividing cache lines into at least most significant portions and next most significant portions, storing cache line contents in a register array so that the most significant portion of each cache line is stored in a first row of the register array and the next most significant portion of each cache line is stored in a second row of the register array. Contents of a first register portion of the first row may be provided to a barrel shifter where the contents may be aligned and then stored in a buffer. | 01-31-2013 |
Karthikeyan Vaithianathan, Beaverton, OR US
Patent application number | Description | Published |
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20110093518 | NEAR OPTIMAL CONFIGURABLE ADDER TREE FOR ARBITRARY SHAPED 2D BLOCK SUM OF ABSOLUTE DIFFERENCES (SAD) CALCULATION ENGINE - Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network. | 04-21-2011 |
20130262816 | TRANSLATION LOOKASIDE BUFFER FOR MULTIPLE CONTEXT COMPUTE ENGINE - Some implementations disclosed herein provide techniques and arrangements for an specialized logic engine that includes translation lookaside buffer to support multiple threads executing on multiple cores. The translation lookaside buffer enables the specialized logic engine to directly access a virtual address of a thread executing on one of the plurality of processing cores. For example, an acceleration compute engine may receive one or more instructions from a thread executed by a processing core. The acceleration compute engine may retrieve, based on an address space identifier associated with the one or more instructions, a physical address associated with the one or more instructions from the translation lookaside buffer to execute the one or more instructions using the physical address. | 10-03-2013 |
Karthikeyan Yuvarej, St. Louis, MO US
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20150352721 | Truck Unloader Visualization - Methods, devices, systems, and non-transitory process-readable storage media for a computing device of a robotic carton unloader to identify items to be unloaded from an unloading area within imagery. | 12-10-2015 |