| Patent application number | Description | Published |
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| 20090323511 | Combined OFDMA Preamble Index Identification, Integer Frequency Offset Estimation, and Preamble CINR Measurement - A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs. | 12-31-2009 |
| 20090323512 | Combined OFDMA Preamble Index Identification, Integer Frequency Offset Estimation, and Preamble CINR Measurement - A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs. | 12-31-2009 |
| 20100131577 | Programmable CORDIC Processor - A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input. | 05-27-2010 |
| 20100138631 | Process for QR Transformation using a CORDIC Processor - A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input. | 06-03-2010 |
| 20100138632 | Programmable CORDIC Processor with Stage Re-Use - A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input. | 06-03-2010 |
| 20100202504 | Channel Estimation Filter for OFDM receiver - A channel smoothing filter with a finite impulse response (FIR) has a controller which reads parallel sample data out of an FFT memory in such a manner as to generate an even function, the sample data applied to a preamble equalizer accompanied by a preamble sign and zero, the preamble outputs coupled to three filter processors, each filter processor having four filter engines whose outputs are summed, the channel smoothing filter generating an a register output, the register input coupled to a summer which has as inputs: the first filter processor shifted by four, the second filter processor shifted by two, the third filter processor, and the register output. Coefficients for an edge filter and a central filter are provided in Zero Sign Shift (ZSS) format, and by selection of coefficients using a canonical signed digit (CSD) algorithm, no multipliers are required for the channel smoothing FIR filter. | 08-12-2010 |
| Patent application number | Description | Published |
|---|
| 20090304103 | Power Allocation Method for MIMO Transmit Beamforming - A transmit power allocation method for computing a transmit beamforming W matrix for a N streams of data, the method has a first step of measuring a receive channel characteristic H matrix, a second step of decomposing the H matrix into a U matrix which is formed from the left eigenvectors of the H matrix, an Σ matrix which is a diagonal matrix formed from the square roots of the eigenvalues of said H matrix and re-ordered by strength, and a V | 12-10-2009 |
| 20100027604 | Preamble detection in a Multi-Antenna MIMO 802.16e Receiver - A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect. | 02-04-2010 |
| 20100027718 | Preamble detection in a Multi-Antenna MIMO 802.16e Receiver - A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect. | 02-04-2010 |
| 20100046645 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
| 20100046646 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
| 20100046647 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
| 20100046648 | Interpolation IIR filter for OFDM Baseband Processing - A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier. | 02-25-2010 |
