Kariyazaki
Hirokazu Kariyazaki, Fukuoka JP
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20100292843 | ROBOT SYSTEM - A robot system includes a robot and a robot controller including a drive unit, a memory that stores an arm-occupied region and a movement-forbidden region, a target position calculation unit that outputs a target position of a tool or a workpiece, a movement-forbidden region entry monitoring unit that checks whether the arm-occupied region based on the target position enters the movement-forbidden region and outputs a stop request if it is checked that the arm-occupied region enters the movement-forbidden region, and a predicted-coasting-position calculating unit that calculates a predicted coasting position of each axis and a coasting position of the tool or the workpiece in the case that the robot is urgently stopped. The movement-forbidden region entry monitoring unit checks whether the arm-occupied region at the coasting position enters the movement-forbidden region and outputs another stop request if it is checked that the arm-occupied region enters the movement-forbidden region. | 11-18-2010 |
20110224826 | ROBOT SYSTEM - A process includes defining, in a memory, arm-occupied regions including robot arms and a workpiece and tool attached to a robot wrist, a virtual safety protection barrier with which the arms are not allowed to come into contact, and movable ranges of robot axes; estimating the coasting angle of each robot axis for which the axis will coast when the robot is stopped due to an emergency stop while moving to a next target position, from an actually measured amount of coasting and the like; determining a post-coasting predicted position of the robot by adding the estimated coasting angles to the next target position; checking whether or not the arm-occupied regions at the post-coasting predicted position will come into contact with the virtual safety protection barrier, or whether or not the robot axes are within the movable ranges; and performing control to stop the robot immediately upon detection of abnormality. | 09-15-2011 |
Makoto Kariyazaki, Kakogawa-Shi JP
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20090246067 | HIGH-STRENGTH STEEL SHEET EXCELLENT IN RESISTANCE TO STRESS-RELIEF ANNEALING AND IN LOW-TEMPERATURE JOINT TOUGHNESS - A high-strength steel sheet according to the present invention not only is suitably adjusted in its chemical elements composition, but also has a DE value defined by the following Equation (1) of 0.0340% or more, and a carbon equivalent Ceq defined by the following Equation (2) of 0.45% or less: | 10-01-2009 |
20110020167 | HIGH-STRENGTH THICK STEEL PLATE FOR STORAGE CONTAINER EXCELLENT IN LOW-TEMPERATURE TOUGHNESS OF MULTI-LAYER WELDED JOINT - The high-strength thick steel plate for storage container contains: C: 0.12-0.16% (means mass %, hereinafter the same), Si: 0.05-0.5%, Mn: 1-1.5%, Al: 0.01-0.05%, Nb: 0.003-0.02%, Mo: 0.03-0.3%, V: 0.025-0.04%, Cr: 0.05-0.3%, Cu: 0.05-0.5%, Ni: 0.15-0.55%, Ca: 0.0005-0.006% respectively, and the RP value as defined by an equation (1) below satisfies the relation of RP≧4.5×10 | 01-27-2011 |
Makoto Kariyazaki, Hyogo JP
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20100322814 | HIGH-STRENGTH STEEL SHEET EXCELLENT IN RESISTANCE TO STRESS-RELIEF ANNEALING AND LOW TEMPERATURE JOINT TOUGHNESS - A high-strength steel sheet is provided which, even when subjected to long-term stress-relief annealing after welding, decreases little in strength and which has satisfactory low-temperature HAZ toughness. The high-strength steel sheet has a chemical composition adequately regulated and has a CP value defined by the following equation (1) of 5.40% or higher and a carbon equivalent (Ceq) defined by the following equation (2) of 0.45% or lower. CP value=125[Ti]+111[Nb]+60[V]+15[Mo] (1) ([Ti], [Nb], [V], and [Mo] indicate the contents (mass %) of Ti, Nb, V, and Mo, respectively.) Ceq=[C]+[Mn]/6+([Cr]+[Mo]+[V])/5+([Cu]+[Ni])/15 (2) ([C], [Mn], [Cr], [Mo], [V], [Cu], and [Ni] indicate the contents (mass %) of C, Mn, Cr, Mo, V, Cu, and Ni, respectively.) | 12-23-2010 |
Shuuichi Kariyazaki, Kanagawa JP
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20100109152 | Electronic device and lid - The present invention can prevent a lid from tilting when the lid is attached to a substrate. An electronic device | 05-06-2010 |
20110235298 | Wiring substrate and method of manufacturing the wiring substrate - A wiring substrate includes a side-wall electroconduction layer and a land. The side-wall electroconduction layer is formed on the side-wall of a through hole formed in the substrate. The land is an electroconduction layer connected with the side-wall electroconduction layer in which only the land portion as a minimum necessary portion used for wiring is formed to the surface of the substrate. Unnecessary portion of the land other than the land portion is eliminated. | 09-29-2011 |
20130077275 | ELECTRONIC DEVICE, WIRING SUBSTRATE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - Even in an electronic device where electrodes are coupled electrically using a solder, sections to which electrodes of an electronic component are coupled are switched by a method other than changing circuits of the electronic component or changing circuits of a wiring substrate. | 03-28-2013 |
20150061104 | SEMICONDUCTOR DEVICE - An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other. | 03-05-2015 |
Shuuichi Kariyazaki, Kawasaki-Shi JP
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20140159224 | SEMICONDUCTOR DEVICE - A semiconductor device in which warpage is less likely to occur. In the semiconductor device, two semiconductor chips are mounted over a diagonal of a substrate and one of the semiconductor chips lies over the intersection of the two diagonals of the substrate. The semiconductor device gives a solution to the following problem. In order to implement a semiconductor device with a plurality of semiconductor chips mounted on a substrate, generally the substrate must have a larger area. If the area of the substrate is increased without an increase in its thickness, warpage or deformation of the semiconductor device is more likely to occur. It is difficult or impossible to mount a warped or deformed semiconductor device over a wiring substrate. | 06-12-2014 |
20140300003 | SEMICONDUCTOR DEVICE AND INTERCONNECT SUBSTRATE - A semiconductor substrate includes a semiconductor chip and an interconnect substrate. The interconnect substrate has an interconnect region between a first main surface formed with plural orderly arranged first and second signal electrodes connected to the semiconductor chip, and a second main surface. The interconnect region has a core substrate, interconnect layers formed on both surfaces thereof, plural first through holes and plural first vias that pass through the interconnect layer on the side of the first main surface for forming impedance matching capacitances. Each first through hole is connected to a first signal interconnect at a position spaced part from the first signal electrode by a first interconnect length and each first via is connected to the second signal interconnect at a position spaced apart from the second signal electrode by a second interconnect length that is substantially equal with the first interconnect length. | 10-09-2014 |
20150076684 | Semiconductor Device - A semiconductor device includes a main surface, a back surface opposite to the main surface, a first side on the main surface, a second side opposite to the first side, a third side between the first side and the second side, a fourth side opposite to the third side, a first point on a periphery of the main surface between the first side and the third side, a second point on the periphery of the main surface between the second side and the fourth side, a third point on the periphery of the main surface between the first side and the fourth side, and | 03-19-2015 |
Syuuichi Kariyazaki, Tokyo JP
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20100176504 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased. | 07-15-2010 |
20120068362 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MEMBER AND MOUNTING MEMBER - A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased. | 03-22-2012 |