Patent application number | Description | Published |
20100060310 | Systems and Methods Utilizing Redundancy in Semiconductor Chip Interconnects - An integrated circuit, or combination of integrated circuits, has a primary interconnect, a redundant interconnect, and circuitry connecting the primary and redundant interconnects allowing selection of the redundant interconnect to bypass the primary interconnect. | 03-11-2010 |
20120068734 | Integrated Circuit Leakage Power Reduction using Enhanced Gated-Q Scan Techniques - Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool. | 03-22-2012 |
20130043897 | TESTING STACKED DIE - An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die. | 02-21-2013 |
20130241593 | INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES - Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool. | 09-19-2013 |
20140181771 | METHOD AND APPARATUS FOR ENHANCED STATIC IR DROP ANALYSIS - Methods and apparatus for Enhanced Static IR Drop Analysis are provided. Enhanced Static IR Drop Analysis can be used to determine a quality and robustness of a power distribution network in a circuit. In examples, Enhanced Static IR Drop Analysis includes recording time points at which global current demand profile peaks, sampling instantaneous current from individual tile-based current demand profiles at each time point, and running Static IR Analysis for the tiles at the time points to determine tile current use by the tiles during the time points. Enhanced Static IR Drop Analysis can be used for quick assessment of peak current distribution and determining how the peak current distribution stresses the power distribution network. Enhanced Static IR Drop Analysis is useful during earlier stages of circuit design, when quickly producing circuit performance data is imperative and conventional techniques require significant resources. | 06-26-2014 |
20140223389 | SYSTEM AND METHOD TO DESIGN AND TEST A YIELD SENSITIVE CIRCUIT - A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops. | 08-07-2014 |
20150145575 | SPINTRONIC LOGIC GATES EMPLOYING A GIANT SPIN HALL EFFECT (GSHE) MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT(S) FOR PERFORMING LOGIC OPERATIONS, AND RELATED SYSTEMS AND METHODS - Aspects described herein are related to spintronic logic gates employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a spintronic logic gate is disclosed that includes a charge current generation circuit and a GSHE MTJ element. The charge current generation circuit is configured to generate a charge current representing an input bit set. The input bit set may include one or more input bit states for a logical operation. The GSHE MTJ element is configured to set a logical output bit state for the logical operation, and has a threshold current level. The GSHE MTJ element is configured to generate a GSHE spin current in response to the charge current and perform the logical operation on the input bit set by setting the logical output bit state based on whether the GSHE spin current exceeds the threshold current level. | 05-28-2015 |
20150145576 | SPINTRONIC LOGIC GATES EMPLOYING A GIANT SPIN HALL EFFECT (GSHE) MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT(S) FOR PERFORMING LOGIC OPERATIONS, AND RELATED SYSTEMS AND METHODS - Aspects described herein are related to pipeline circuits employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a pipeline circuit is disclosed. The pipeline circuit includes a first pipeline stage and a second pipeline stage. The first pipeline stage is configured to store a first bit set and to generate a first charge current representing the first bit set. The second pipeline stage includes a first GSHE MTJ element. The first GSHE MTJ element is configured to set a first bit state for the first logical operation, and has a first threshold current level. The first GSHE MTJ element is configured to generate a first GSHE spin current in response to the first charge current. In this manner, the first GSHE MTJ element is also configured to perform the first logical operation on the first bit set. | 05-28-2015 |