Patent application number | Description | Published |
20130003408 | SYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING CIRCULAR TIP AND BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second circular base segments with a second contact angle, the second contact angle being less than the first contact angle and the second contact angle being equal to each other. Further, the circular tip segment satisfies the following equation: | 01-03-2013 |
20130003413 | SYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being less than the first contact angle and the second contact angle being equal to each other and | 01-03-2013 |
20130003414 | SYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being greater than the first contact angle and the second contact angle being equal to each other and | 01-03-2013 |
20130063974 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING CIRCULAR BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a first and second circular tip segment each circular tip segment with a first contact angle, and a first and second circular base segment each circular base segment with a top and bottom contact angle, the contact angles of the circular base segments being greater than the contact angle of the circular tip segments. Further, the circular tip segments satisfies the following equations: | 03-14-2013 |
20130063975 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being greater than the first contact angle and the second contact angle being equal to each other and wherein the first and second circular tip segments satisfy the following equations respectively: | 03-14-2013 |
20130063976 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING CIRCULAR BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a first and second circular tip segment each circular tip segment with a first contact angle, and a first and second circular base segment each circular base segment with a top and bottom contact angle, the contact angles of the circular base segments being less than the contact angle of the circular tip segments. Further, the circular tip segment satisfies the following equations: | 03-14-2013 |
20130063977 | ASYMMETRIC SERRATED EDGE LIGHT GUIDE FILM HAVING ELLIPTICAL BASE SEGMENTS - The present invention provides a planar light guide film for a backlight unit having at least one point light source, the light guide film comprising a light input surface for receiving light from the point light source, a light redirecting surface for redirecting light received from the light input surface and a light output surface for outputting at least the light redirected from the light redirecting surface. The light input surface further comprises a composite lens structure having a circular tip segment with a first contact angle, and a first and second elliptical base segments with a second contact angle, the second contact angle being less than the first contact angle and the second contact angle being equal to each other and | 03-14-2013 |
Patent application number | Description | Published |
20110027956 | Method of Fabricating a Device Using Low Temperature Anneal Processes, a Device and Design Structure - A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device. | 02-03-2011 |
20110042731 | STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM - A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures. | 02-24-2011 |
20120180010 | METHOD OF FABRICATING A DEVICE USING LOW TEMPERATURE ANNEAL PROCESSES, A DEVICE AND DESIGN STRUCTURE - A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device. | 07-12-2012 |
Patent application number | Description | Published |
20090146223 | PROCESS AND METHOD TO LOWER CONTACT RESISTANCE - A method removes the spacers from the sides of a transistor gate stack, and after the spacers are removed, the method implants an additional impurity into surface regions of the substrate not protected by the gate conductor (or alternatively just amorphizes these surface regions, without adding more impurity). The method then performs a laser anneal on the additional impurity (to activate the additional impurity) or amorphized regions (to recrystallize the amorphized regions). After this, permanent spacers are formed on the sidewalls of the gate conductor. Then, the surface regions of the substrate not protected by the gate conductor and the permanent spacers are silicided, to create silicide source/drain regions. This forms the silicide regions in the additional impurity or in the recrystallized amorphized regions to reduce the source/drain resistance by improving the active dopant concentration at the silicon-silicide interface. | 06-11-2009 |
20090148988 | METHOD OF REDUCING EMBEDDED SIGE LOSS IN SEMICONDUCTOR DEVICE MANUFACTURING - Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET. | 06-11-2009 |
20120083092 | STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM - A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures. | 04-05-2012 |
20120104547 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure. | 05-03-2012 |
20120175694 | STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM - A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor. | 07-12-2012 |
20120184075 | REDUCING DISLOCATION FORMATION IN SEMICONDUCTOR DEVICES THROUGH TARGETED CARBON IMPLANTATION - A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail. | 07-19-2012 |
20120261797 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI. | 10-18-2012 |
20130134490 | LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR - A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode. | 05-30-2013 |
20130260520 | LOW RESISTANCE EMBEDDED STRAP FOR A TRENCH CAPACITOR - A trench is formed in a semiconductor substrate, and is filled with a node dielectric layer and at least one conductive material fill portion that functions as an inner electrode. The at least one conductive material fill portion includes a doped polycrystalline semiconductor fill portion. A gate stack for an access transistor is formed on the semiconductor substrate, and a gate spacer is formed around the gate stack. A source/drain trench is formed between an outer sidewall of the gate spacer and a sidewall of the doped polycrystalline semiconductor fill portion. An epitaxial source region and a polycrystalline semiconductor material portion are simultaneously formed by a selective epitaxy process such that the epitaxial source region and the polycrystalline semiconductor material portion contact each other without a gap therebetween. The polycrystalline semiconductor material portion provides a robust low resistance conductive path between the source region and the inner electrode. | 10-03-2013 |
20140084418 | LATERAL EPITAXIAL GROWN SOI IN DEEP TRENCH STRUCTURES AND METHODS OF MANUFACTURE - Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer including a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer including a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI. | 03-27-2014 |
20140213053 | SEMICONDUCTOR DEVICE INCLUDING SUBSTRATE CONTACT AND RELATED METHOD - A method of forming a contact on a semiconductor device is disclosed. The method includes: forming a mask on the semiconductor device, the mask exposing at least one contact node disposed within a trench in a substrate of the semiconductor device; performing a first substrate contact etch on the semiconductor device, the first substrate contact etch recessing the exposed contact node within the trench; removing a set of node films disposed above the exposed contact node and on the sides of the trench; and forming a contact region within the trench above the exposed contact node, the contact region contacting the substrate. | 07-31-2014 |
Patent application number | Description | Published |
20100246792 | Administering Participant Attendance Of Teleconferences - Computer-implemented methods, apparatus, and products for administering participant attendance of teleconferences, including monitoring, by a teleconference administration device comprising one or more modules of automated computing machinery, present call status of a user's telephone; determining, by the teleconference administration device in dependence upon one or more calendar events representing previously scheduled teleconferences, whether the present call status of the user's telephone conflicts with a previously scheduled teleconference; and if the present call status of the user's telephone conflicts with a previously scheduled teleconference, notifying, by the teleconference administration device, prospective participants of the conflict. | 09-30-2010 |
20100262610 | Identifying Subject Matter Experts - Identifying subject matter experts including receiving, by an SME search engine from a user, a search request including text corresponding to a particular subject matter; finding, in one or more information repositories, in dependence upon the text of the search request, one or more resources, including determining for each resource a credibility rating; identifying one or more potential subject matter experts associated with the resources; calculating, for each of the potential subject matter experts, in dependence upon the credibility rating of the each resource, a weighted expert score representing an estimated level of expertise for each potential subject matter expert; and returning, to the user by the SME search engine as one more search results, the potential subject matter experts in order of the weighted expert scores along with resources associated with the potential subject matter experts. | 10-14-2010 |
Patent application number | Description | Published |
20100048261 | Multifunctional Keyboard For A Mobile Communication Device And Method Of Operating The Same - An apparatus and method for telephony tone signal and character code generation for QWERTY keyboards includes a QWERTY style keyboard, a processor and a keyboard mode control software module. The QWERTY style keyboard has a plurality of letter keys, wherein each letter key is configured to generate a unique input signal. The processor is coupled to the keyboard and is configured to convert each unique input signal generated by the letter keys into a character code and/or a telephony tone signal. The keyboard mode control software module operates on the processor, and controls whether the processor converts the unique input signals from the letter keys into character codes or telephony tone signals. | 02-25-2010 |
20110032125 | MULTIFUNCTIONAL KEYBOARD FOR A MOBILE COMMUNICATION DEVICE AND METHOD OF OPERATING THE SAME - An apparatus and method for telephony tone signal and character code generation for QWERTY keyboards includes a QWERTY style keyboard, a processor and a keyboard mode control software module. The QWERTY style keyboard has a plurality of letter keys, wherein each letter key is configured to generate a unique input signal. The processor is coupled to the keyboard and is configured to convert each unique input signal generated by the letter keys into a character code and/or a telephony tone signal. The keyboard mode control software module operates on the processor, and controls whether the processor converts the unique input signals from the letter keys into character codes or telephony tone signals. | 02-10-2011 |
20110043385 | MULTIFUNCTIONAL KEYBOARD FOR A MOBILE COMMUNICATION DEVICE AND METHOD OF OPERATING THE SAME - An apparatus and method for telephony tone signal and character code generation for QWERTY keyboards includes a QWERTY style keyboard, a processor and a keyboard mode control software module. The QWERTY style keyboard has a plurality of letter keys, wherein each letter key is configured to generate a unique input signal. The processor is coupled to the keyboard and is configured to convert each unique input signal generated by the letter keys into a character code and/or a telephony tone signal. The keyboard mode control software module operates on the processor, and controls whether the processor converts the unique input signals from the letter keys into character codes or telephony tone signals. | 02-24-2011 |
20110304552 | MULTIFUNCTIONAL KEYBOARD FOR A MOBILE COMMUNICATION DEVICE AND METHOD OF OPERATING THE SAME - An apparatus and method for telephony tone signal and character code generation for QWERTY keyboards includes a QWERTY style keyboard, a processor and a keyboard mode control software module. The QWERTY style keyboard has a plurality of letter keys, wherein each letter key is configured to generate a unique input signal. The processor is coupled to the keyboard and is configured to convert each unique input signal generated by the letter keys into a character code and/or a telephony tone signal. The keyboard mode control software module operates on the processor, and controls whether the processor converts the unique input signals from the letter keys into character codes or telephony tone signals. | 12-15-2011 |
20140243047 | MULTIFUNCTIONAL KEYBOARD FOR A MOBILE COMMUNICATION DEVICE AND METHOD OF OPERATING THE SAME - An apparatus and method for telephony tone signal and character code generation for QWERTY keyboards includes a QWERTY style keyboard, a processor and a keyboard mode control software module. The QWERTY style keyboard has a plurality of letter keys, wherein each letter key is configured to generate a unique input signal. The processor is coupled to the keyboard and is configured to convert each unique input signal generated by the letter keys into a character code and/or a telephony tone signal. The keyboard mode control software module operates on the processor, and controls whether the processor converts the unique input signals from the letter keys into character codes or telephony tone signals. | 08-28-2014 |
Patent application number | Description | Published |
20080253284 | Controlling a Transmission Rate of Packet Traffic - Controlling a transmission rate of packet traffic includes receiving packets from a network processor. The packets are stored in a buffer associated with a processor. If an occupancy level of the buffer is greater than a predetermined threshold, it is determined that the processor is congested. A message is transmitted to the network processor indicating the processor is congested. | 10-16-2008 |
20130036152 | LOOKUP FRONT END PACKET OUTPUT PROCESSOR - A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host. | 02-07-2013 |
20140188973 | LOOKUP FRONT END PACKET OUTPUT PROCESSOR - A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. The lookup front-end further processes the response message and provides a corresponding response to the host. | 07-03-2014 |
20140269718 | PACKET EXTRACTION OPTIMIZATION IN A NETWORK PROCESSOR - A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. A lookup front-end receives lookup requests from a host, and processes these lookup requests to generate key requests for forwarding to the lookup engines. Based on information in the packet, the lookup front-end can optimize start times for sending key requests as a continuous stream with minimal delay. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found. | 09-18-2014 |
20140281834 | Method and Apparatus for Data Integrity Checking in a Processor - In an embodiment, a method of handling data packets within a processor includes intercepting, by a hardware packet integrity checking module, one or more data fields associated with a current segment of a data packet being forwarded from a first hardware entity operating in a cut-through mode to one or more processing clusters, where at least one data field of the one or more data fields is indicative of an operation associated with the data packet. At the hardware error detection module, integrity of the current segment of the data packet is checked based on the one or more data fields and parameters corresponding to the operation associated with the data packet. At least one data field of the one or more data fields is modified upon detecting an integrity error. The data fields are forwarded to the one or more processing clusters. | 09-18-2014 |
Patent application number | Description | Published |
20090044169 | METHOD, FRAMEWORK, AND PROGRAM PRODUCT FOR FORMATTING AND SERVING WEB CONTENT - The present invention provides an approach and corresponding framework that separates data from its formatting/view by generating the dynamic JavaScript (data) as a set (e.g., at least one) of JavaScript (data) objects, without any HTML formatting. Then, a set of JavaScript functions can be created that takes the set of JavaScript objects as a parameter, and outputs all or a subset of this data object in a format determined by this JavaScript function. In general, these formatting functions can be static, rather than dynamic, JavaScript. This approach has the advantage of providing a much greater degree of formatting flexibility, without the need for each new format to establish a connection with the back-end system providing the data. | 02-12-2009 |
20120311186 | METHOD, FRAMEWORK, AND PROGRAM PRODUCT FOR FORMATTING AND SERVING WEB CONTENT - The present invention provides an approach and corresponding framework that separates data from its formatting/view by generating the dynamic JavaScript (data) as a set (e.g., at least one) of JavaScript (data) objects, without any HTML formatting. Then, a set of JavaScript functions can be created that takes the set of JavaScript objects as a parameter, and outputs all or a subset of this data object in a format determined by this JavaScript function. In general, these formatting functions can be static, rather than dynamic, JavaScript. This approach has the advantage of providing a much greater degree of formatting flexibility, without the need for each new format to establish a connection with the back-end system providing the data. | 12-06-2012 |