Patent application number | Description | Published |
20080245559 | Variable interconnect geometry for electronic packages and fabrication methods - Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed. | 10-09-2008 |
20080305653 | Complant off-chip interconnects for use in electronic packages and fabrication methods - Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed. | 12-11-2008 |
20090188705 | Construction of Reliable Stacked Via in Electronic Substrates - Vertical Stiffness Control Method - A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the platted through hole landing. | 07-30-2009 |
20090189289 | EMBEDDED CONSTRAINER DISCS FOR RELIABLE STACKED VIAS IN ELECTRONIC SUBSTRATES - A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via. | 07-30-2009 |
20090189290 | CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES - A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias. | 07-30-2009 |
20120192418 | Compliant Off-Chip Interconnects for Use in Electronic Packages and Fabrication Methods - Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed. | 08-02-2012 |
20120267158 | CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD - A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern. | 10-25-2012 |
20120279061 | CLUSTERED STACKED VIAS FOR RELIABLE ELECTRONIC SUBSTRATES - A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias. | 11-08-2012 |
20120299195 | CONSTRUCTION OF RELIABLE STACKED VIA IN ELECTRONIC SUBSTRATES - VERTICAL STIFFNESS CONTROL METHOD - A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface. | 11-29-2012 |