| Patent application number | Description | Published |
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| 20120242523 | CHARGE REDISTRIBUTION DIGITAL-TO-ANALOG CONVERTER - Embodiments of the present disclosure may provide a charge redistribution DAC with an on-chip reservoir capacitor to provide charges to the DAC in lieu of traditional external reference voltages. The DAC may include the on-chip reservoir capacitor having a first plate and a second plate, an array of DAC capacitors to generate a DAC output, and an array of switches controlled by a DAC input word to couple the DAC capacitors to the reservoir capacitor. The charge redistribution DAC may further comprise a first switch connecting the first plate to an external terminal for a first external reference voltage, and a second switch connecting the second plate to an external terminal for a second external reference voltage. One embodiment may provide an ADC that includes the charge redistribution DAC. | 09-27-2012 |
| 20120262315 | SELF-TIMED DIGITAL-TO-ANALOG CONVERTER - A tracking module that tracks the operation of a digital-to-analog converter (DAC). The DAC tracking module may be included on-chip with a DAC, and be formed with similar circuit components as a DAC. The DAC tracking circuit may output a signal indicating that the DAC within a SAR ADC has settled to an approximate value during each bit conversion. A differential solution is also provided. Power may be optimized because optimal conversion speed may be achieved, and a comparator within the DAC may be turned off or placed in a standby mode at the end of bit conversions, and before the next conversion cycle in response to the signal output by the DAC tracking module. | 10-18-2012 |
| 20120268185 | COMPARATOR WITH ADAPTIVE TIMING - An adaptive delay device that provides a delay to a signal based on circuit conditions such as temperature, supply voltage values and/or fabrication processes. The adaptive delay device may respond to circuit conditions by charging a capacitive device to a threshold voltage. A comparator may incorporate the adaptive delay device to provide adaptive timing for the comparator functions thereby attaining improved noise performance and/or reduce power consumption. | 10-25-2012 |
| 20120274488 | PRE-CHARGED CAPACITIVE DIGITAL-TO-ANALOG CONVERTER - Embodiments of the present disclosure may provide a charge redistribution DAC with two sets of capacitors that provides a DAC output by sharing charges between a plurality of pairs of capacitors in lieu of charging the capacitors using traditional external reference voltages. The charge redistribution DAC may comprise a plurality of pairs of first and second capacitors that each has a first side and a second side, and a group of first switches and a group of second switches. Each first or second switch selectively controls connection of the first side of a respective first or second capacitor to one of a pair of output signal lines according to a DAC input word. The charge redistribution DAC further may comprise a group of bridging switches each connected between second sides of paired first and second capacitors. | 11-01-2012 |
| Patent application number | Description | Published |
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| 20090085661 | METHODS AND APPARATUS FOR PROCESS INVARIANT TRANSCONDUCTANCE - In one aspect, a resistor process invariant transconductor is provided. The transconductor comprises a voltage input configured to receive at least one voltage signal, a current output configured to provide at least one current signal, wherein a ratio between the at least one voltage signal and the least one current signal forms a total transconductance for the transconductor, and a circuit including at least one integrated resistor connected between the voltage input and the current output, the circuit adapted to maintain the total transconductance substantially constant across variation of the at least one integrated resistor. | 04-02-2009 |
| 20100090875 | Dithering Technique For Reducing digital Interference - The invention is directed to a circuit and method for equalizing digital interference. A digital interference equalizing circuit may include a signal clipping unit, receiving a digital signal and clipping the digital signal based upon a clipping function, and a dithering unit adding dither to the clipped digital signal. A digital interference equalizing circuit may also include a noise detection circuit, detecting the normal activity level in a digital signal which may then be used to scale the dither added to the digital signal. | 04-15-2010 |
| 20100127750 | SWITCHED CAPACITOR INPUT STAGE FOR IMAGING FRONT-ENDS - Embodiments of the present invention provide an apparatus and control method for an analog front end (AFE) amplifier for controlling DC restore operations. According to the exemplary method, a first input stage of the AFE is controlled to operate as a continuous time amplifier that has high input impedance and draws substantially no input leakage current for a first predetermined area of an imaging sensor image array. The first input stage is controlled to operate as a sample and hold amplifier with DC restore functionality for a second predetermined area of the imaging sensor image array. According to an embodiment, the AFE input stage operates as a continuous time amplifier when reading pixels from the sensor's active image array but operates as a sample and hold amplifier with DC restore when reading pixels from the image array that correspond to so-called ‘black-level’ pixels or pixels that otherwise fall outside the sensor's active image field. | 05-27-2010 |
| 20100148878 | AMPLIFIER WITH DITHER - An analog amplifier includes at least one signal path. Each of the at least one signal path extends between an input and an output and includes a load device coupled to the output and a transistor coupled to the input. The analog amplifier further includes a dither current source selectively coupled to one of the at least one signal path. The dither current source is capable of supplying dither current to the load device of the selected signal path directly by bypassing the transistor of the selected signal path. | 06-17-2010 |
| 20100149360 | SYSTEM AND METHOD FOR ISOLATED NMOS-BASED ESD CLAMP CELLDITHERING TECHNIQUES TO REDUCE MISMATCH IN MULTI-CHANNEL IMAGING SYSTEMS - An embodiment of the present invention may be directed to a multi channel imaging system. The multi channel imaging system may include an input for a light signal and a plurality of channel circuits. Each of the channel circuits may have an analog signal processing chain converting some portion of the light signal into to a digital representation, the plurality of channel circuits may operate in parallel. The multi channel imaging system may further comprise at least one dither circuit coupled to a point in at least one of the analog signal processing chains to add dither. | 06-17-2010 |
| 20100176979 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter comprising an Nth analog to digital converter and an N+1th analog to digital converter arranged in series such that a residue signal from the Nth analog to digital converter is provided as an input to the N+1th analog to digital converter, characterised in that a bandwidth control means is provided in a signal path for the residue signal and the bandwidth control means is controlled so as to have a first bandwidth during a first period following generation of a conversion result from the Nth analog to digital converter, and a second bandwidth less than the first bandwidth in a second period following the first period. | 07-15-2010 |
| 20100327925 | CALIBRATING MULTIPLYING-DELAY-LOCKED-LOOPS (MDLLS) - Devices and methods for varying individual periods or cycle times of upconverted clock signals within a corresponding reference clock cycle are disclosed. In some embodiments, these varying cycle times may improve signal synchronization between the upconverted clock and the reference clock. In different embodiments, different types of counters and counting circuits keep track of the number of elapsed upconverted clock cycles in order to determine the specific upconverted clock cycles with longer cycle times. In some embodiments, a signal may be sent to a delay line to change the amount of delay between upconverted clock pulses, thereby increasing or decreasing a specific upconverted clock cycle time or period. In some embodiments the specific upconverted clock cycle(s) changed in each reference clock cycle may vary, which may further improve reconciliation between the upconverted clock cycles and the corresponding reference clock cycle. | 12-30-2010 |
| 20100327934 | DIGITAL DELAY LINES - Some embodiments provide real-time variable delays in a delay line. In some of these embodiments, the real-time variable delays may be enable without producing clock glitches. In an embodiment, delay cells in a delay line may be coupled together in a chain to form a lattice of inverters providing different paths of signal propagation. Each path may have a different number of inverters; each inverter adding a known processing time associated with the signal inversion process. In some embodiments, an input signal may be propagated in an inverted or non-inverted form to the inputs of multiple inverters in the lattice, including the inputs of inverters through which the input signal does not propagate. A desired delay time may be obtained in an embodiment by selecting a path containing a desired number and configuration of inverters. The path may be selected in an embodiment using switchably enabled inverters. | 12-30-2010 |
