Patent application number | Description | Published |
20100079061 | LIGHT EMITTING DIODE DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of an LED device includes the following steps. First, a substrate and at least one LED disposed on the substrate are provided. Next, a porous material layer having a plurality of pores is formed on a surface of the LED. Finally, a plurality of nanocrystals are formed in the pores to construct a phosphor layer on the surface of the LED. | 04-01-2010 |
20100237360 | LIGHT EMITTING DIODE AND BACK LIGHT MODULE THEREOF - A light emitting diode (LED) includes an LED chip, a substrate structure, a fluorescence layer, and a lens. The substrate structure includes a cavity. The fluorescence layer covers on the LED chip and is configured in the cavity and covering the LED chip. The lens is installed on the substrate structure. The lens includes a curved lateral wall, a plane at the top, and a conical concave portion at the top center. | 09-23-2010 |
20110019397 | LIGHT EMITTING DIODE, BACKLIGHT MODULE, AND LIGHT TUBE - A light emitting diode includes: a base with a concave portion; a light emitting chip disposed in the concave portion; an encapsulating layer filled in the concave portion; and an optical adjusting element disposed on the light emitting chip. Herein, the light emitting diode has a batwing distribution in a horizontal view angle, and the light emitting diode has a Lambertian distribution in a vertical view angle thereof. | 01-27-2011 |
20120187423 | LIGHT EMITTING DIODE DEVICE - A manufacturing method of an LED device includes the following steps. First, a substrate and at least one LED disposed on the substrate are provided. Next, a porous material layer having a plurality of pores is formed on a surface of the LED. Finally, a plurality of nanocrystals are formed in the pores to construct a phosphor layer on the surface of the LED. | 07-26-2012 |
Patent application number | Description | Published |
20100184255 | MANUFACTURING METHOD FOR PACKAGE STRUCTURE - A manufacturing method for package structure is provided. The manufacturing method includes the follow steps. Firstly, a substrate is provided. Next, a number of chips are provided. Then, the chips are electrically connected with the substrate. After that, the chips are encapsulated with a sealant, so that the chips and the substrate form a package. Then, the package is adhered by a vacuum force. Afterwards, the adhered package is singulated to form many package structures along the portion between adjacent two of airways. | 07-22-2010 |
20100213595 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF AND ENCAPSULATING METHOD THEREOF - A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a flip chip, a plurality of conductive parts and a sealant. The substrate has a substrate upper surface. The flip chip has an active surface and a chip surface opposite to the active surface. The conductive parts electrically connect the substrate upper surface and the active surface. The sealant envelops the flip chip, and the space between the substrate upper surface and the active surface is filled with a portion of the sealant. The sealant further has a top surface. wherein, the chip surface is spaced apart from the top surface by a first distance, the substrate upper surface is spaced apart from the active surface by a second distance, and the ratio of the first distance to the second distance ranges from 2 to 5. | 08-26-2010 |
20110169156 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF AND ENCAPSULATING METHOD THEREOF - A semiconductor package, a manufacturing method thereof and an encapsulating method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a plurality of conductive parts and a sealant. The conductive parts electrically connect an upper surface of the substrate and an active surface of the semiconductor chip. The sealant covers a back surface of the semiconductor chip, wherein the space between the upper surface of the substrate and the active surface of the semiconductor chip is filled with a portion of the sealant. The back surface of the semiconductor is spaced apart from a top surface of the sealant by a first distance, the upper surface of the substrate is spaced apart from the active surface of the semiconductor chip by a second distance, and the ratio of the first distance to the second distance is smaller than or equal to 5. | 07-14-2011 |
20120025369 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor element, a plurality of element contacts and a molding compound. The substrate includes a passivation layer and a plurality of substrate pads. Each substrate pad includes a protrusion and an embedded portion. The embedded portion is embedded in the passivation layer, and the protrusion projects from the passivation layer. The semiconductor element includes a plurality of under bump metallurgies (UBM) with recesses. The ratio of the width of each recess to the first width of the protrusion is larger than 1. The element contacts connect the UBM and the substrate pads. The molding compound covers the semiconductor element. | 02-02-2012 |
20120032351 | SEMICONDUCTOR PACKAGE - A semiconductor package is provided. The semiconductor package includes a substrate, a semiconductor device, a plurality of element contacts, a molding compound and a plurality of substrate contacts. The substrate has opposite to the first surface the first surface and the second surface. The semiconductor device is disposed on the first surface. The element contacts electrically connect the substrate and the semiconductor device. The molding compound encapsulates the semiconductor device and a portion of the molding compound is located between the semiconductor device and the first surface, wherein the molding compound includes a plurality of fillers, the fillers amount to 85-89% of the molding compound and the sizes of the fillers range between 18 and 23 micrometers. The substrate contacts are formed on the second surface. | 02-09-2012 |
Patent application number | Description | Published |
20090075027 | MANUFACTURING PROCESS AND STRUCTURE OF A THERMALLY ENHANCED PACKAGE - A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate. | 03-19-2009 |
20090087947 | FLIP CHIP PACKAGE PROCESS - A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids. | 04-02-2009 |
20100200974 | SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME - A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element. | 08-12-2010 |
Patent application number | Description | Published |
20100223027 | MONITORING METHOD FOR MULTI TOOLS - A monitoring method for multi tools is disclosed. The method includes the steps of providing a plurality of measurement tools for measuring the testing points of standard wafers, calculating a vector for representing a measurement tool, calculating the angle between every two of the vectors and determining the measurement tools having the same performance or not. Thereby, the measurement tools can be efficiently grouped and the measuring stability of the measurement tool is analyzed. | 09-02-2010 |
20100268501 | Method for assessing data worth for analyzing yield rate - A method for assessing data worth for analyzing yield rate includes: getting measured data with data points that corresponds to control variables of semiconductor manufacturing; transforming the data points into a distance matrix with matrix distances corresponding to differences of the data points under the control variables; expressing sample differences recorded in the distance matrix by two-dimension vectors and calculating similarity degrees of the two-dimension vectors and the distance matrix so as to take loss information as a conversion error value; calculating discriminant ability of the transformed two-dimension data and expressing the discriminant ability by an error rate of discriminant; and taking the conversion error value and the error rate of discriminant as penalty terms and calculating a quality score corresponding to the measured data. Thereby, before analyzing the yield rate of semiconductor manufacturing, analysts can determine whether data includes information affecting the yield rate based on the quality score. | 10-21-2010 |
20110010132 | METHOD FOR EVALUATING EFFICACY OF PREVENTION MAINTENANCE FOR A TOOL - A method for evaluating efficacy of prevention maintenance for a tool includes the steps of: choosing a tool which has been maintained preventively and choosing a productive parameter of the tool; collecting values of the productive parameter generated from the tool during a time range for building a varying curve of the productive parameter versus time, modifying the varying curve with a moving average method; transforming the varying curve into a Cumulative Sum chart; and judging whether the values of the productive parameter generated from the tool after the prevention maintenance are more stable, compared with the values of the productive parameter generated from the tool before the prevention maintenance, according to the Cumulative Sum chart. Thereby, if the varying of the values of the productive parameter after the prevention maintenance isn't stable, then the efficacy of this prevention maintenance for the tool is judged not good. | 01-13-2011 |
20110112999 | METHOD FOR PREDICTING AND WARNING OF WAFER ACCEPTANCE TEST VALUE - A method for predicting and warning of WAT value includes the steps as follows. A key process is selected and a WAT value after finishing the key process is used as a predictive goal. A predicting model is built. One batch or plural batches of predictive wafers are prepared, and a Fault Detection and Classification data (FDC data) and a metrology data from the predictive wafers of the key process are collected. The FDC data and the metrology data collected from the predictive wafers are inputted into the predicting model for processing a normal predicting procedure, and a predictive WAT value by the predicting model is outputted. The present invention can accurately predict the WAT value, effectively monitor some specific defective wafers and continuously perform the improvement for the specific defective wafer. | 05-12-2011 |
20110137595 | YIELD LOSS PREDICTION METHOD AND ASSOCIATED COMPUTER READABLE MEDIUM - A yield loss prediction method includes: performing a plurality of types of defect inspections upon a plurality of batches of wafers which begin to be processed during different periods to generate defect inspection data, respectively; for a specific batch of wafers different from the plurality of batches of wafers, calculating defect prediction data of at least one type of defect inspection according to the defect inspection data of at least the type of defect inspections; and predicting a yield loss of the specific batch of wafers according to at least the defect prediction data. | 06-09-2011 |
20120102052 | SPECIFICATION ESTABLISHING METHOD FOR CONTROLLING SEMICONDUCTOR PROCESS - A specification establishing method for controlling semiconductor process, the steps includes: providing a database and choosing a population from the database; sampling a plurality of sample groups from the population, each sample group being a non-normal distribution and having a plurality of samples; filtering the sample groups; summarizing the filtered sample groups to form a non-normal distribution diagram; getting a value-at-risk and a median by calculating from the non-normal distribution diagram; getting a critical value by calculating the value-at-risk and the median with a critical formula; getting a plurality of state values by calculating the filtered sample groups with a proportion formula; and getting an index value by calculating the non-normal distribution diagram with the proportion formula. Thus, the state values indicate the states of the sample groups are abnormal or not by comparing the state values to the index value. | 04-26-2012 |