Patent application number | Description | Published |
20080203468 | FinFET with Reduced Gate to Fin Overlay Sensitivity - Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure. | 08-28-2008 |
20080211054 | METHODS FOR FORMING GERMANIUM-ON-INSULATOR SEMICONDUCTOR STRUCTURES USING A POROUS LAYER AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS - A semiconductor structure that includes a monocrystalline germanium-containing layer, preferably substantially pure germanium, a substrate, and a buried insulator layer separating the germanium-containing layer from the substrate. A porous layer, which may be porous silicon, is formed on a substrate and a germanium-containing layer is formed on the porous silicon layer. The porous layer may be converted to a layer of oxide, which provides the buried insulator layer. Alternatively, the germanium-containing layer may be transferred from the porous layer to an insulating layer on another substrate. After the transfer, the insulating layer is buried between the latter substrate and the germanium-containing layer. | 09-04-2008 |
20080224216 | STRAINED HOT (HYBRID OREINTATION TECHNOLOGY) MOSFETs - A strained HOT MOSFET. The MOSFET includes (a) a first semiconductor layer having a first crystallographic orientation; (b) a buried oxide layer on top of the first semiconductor layer; (c) a second semiconductor layer on top of the buried oxide layer, wherein the second semiconductor layer has a second crystallographic orientation, and wherein the second crystallographic orientation is different from the first crystallographic orientation; (d) a third semiconductor layer on top of the first semiconductor layer, wherein the third semiconductor layer has the first crystallographic orientation; and (e) a fourth semiconductor layer on top of the third semiconductor layer, wherein the fourth semiconductor layer includes a different material than that of the third semiconductor layer, and wherein the fourth semiconductor layer has the first crystallographic orientation. | 09-18-2008 |
20080230822 | VERTICAL TRENCH MEMORY CELL WITH INSULATING RING - A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the semiconductor material region, and where the remaining of the partially etched semiconductor material region defines an insulating ring. A vertical transistor is then formed in the deep trench, such that the vertical transistor is isolated by the insulating ring. A semiconductor structure is also provided. The semiconductor structure includes a first and a second trench memory cells formed on a semiconductor substrate; and an insulating ring surrounding each of the first and second trench memory cells. The insulating ring is configured for significantly enclosing outdiffusions from the trench memory cells. | 09-25-2008 |
20080233691 | METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer. | 09-25-2008 |
20080246068 | TRENCH CAPACITORS AND MEMORY CELLS USING TRENCH CAPACITORS - A trench structure, a method of forming the trench structure, a memory cell using the trench structure and a method of forming a memory cell using the trench structure. The trench structure includes: a substrate; a trench having contiguous upper, middle and lower regions, the trench extending from a top surface of said substrate into said substrate; the upper region of the trench having a vertical sidewall profile; and the middle region of the trench having a tapered sidewall profile. | 10-09-2008 |
20080248625 | METHODS FOR ENHANCING TRENCH CAPACITANCE AND TRENCH CAPACITOR - Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost. | 10-09-2008 |
20080258268 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced. | 10-23-2008 |
20080261128 | Methods and structures for protecting one area while processing another area on a chip - Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. | 10-23-2008 |
20080289651 | METHOD AND APPARATUS FOR WAFER EDGE CLEANING - A wafer edge cleaning system that includes a wafer dry etching chamber and one or more irradiation sources preferably positioned inside the wafer dry etching chamber. The irradiation source such as laser generates a beam aimed at the periphery of the wafer to melt any defects, in particular, black silicon at the edge of the wafer. Preferably, the wafer is mounted on a rotating platform. The invention further provides a method for removing black silicon at the edge of a semiconductor wafer that includes the steps of: patterning the wafer with a trench mask layer; etching the wafer to form a trench thereon; exposing the edge of the wafer to a laser beam to melt the black silicon thereon; stripping the mask and cleaning the wafer. | 11-27-2008 |
20080311708 | HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES - A method for forming a semiconductor structure. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation. | 12-18-2008 |
20090001426 | Integrated Fin-Local Interconnect Structure - Embodiments of the invention generally relate to semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits. | 01-01-2009 |
20090001429 | HYBRID STRAINED ORIENTATED SUBSTRATES AND DEVICES - A semiconductor structure. The structure includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The structure further includes a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials. The second semiconductor region has the first crystallographic orientation, whereas the fourth semiconductor region has the second crystallographic orientation. | 01-01-2009 |
20090001464 | FINFET WITH TOP BODY CONTACT - FinFETs are provided with a body contact on a top surface of a semiconductor fin. The top body contact may be self-aligned with respect to the semiconductor fin and the source and drain regions. Alternately, the source and drain regions may be formed recessed from the top surface of the semiconductor fin. The body or an extension of the body may be contacted above the channel or above one of the source and drain regions. Electrical shorts between the source and drain and the body contacts are avoided by the recessing of the source and drain regions from the top surface of the semiconductor fin. | 01-01-2009 |
20090001480 | HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE - The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) | 01-01-2009 |
20090017584 | PROCESS FOR FINFET SPACER FORMATION - A process for finFET spacer formation generally includes depositing, in order, a conformnal liner material, a conformal spacer material, and a conformal capping material onto the finFET structure; tilt implanting dopant ions into portions of the capping layer about the gate structure; selectively removing undoped capping material about the source and drain regions; selectively removing exposed portions of the spacer material; selectively removing exposed portions of the capping material; anisotropically removing a portion of the spacer material so as to expose a top surface of the gate material and isolate the spacer material to sidewalls of the gate structure; and removing the oxide liner from the fin to form the spacer on the finFET structure. | 01-15-2009 |
20090026491 | TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE - In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor. | 01-29-2009 |
20090047756 | DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR - A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity. | 02-19-2009 |
20090051002 | ELECTRICAL FUSE HAVING A THIN FUSELINK - A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses. | 02-26-2009 |
20090051003 | Methods and Structures Involving Electrically Programmable Fuses - A method for fabricating an eFuse, the method comprising disposing a crystalline silicon eFuse on a substrate having a fuse link portion, a first contact portion, and a second contact portion, wherein the fuse link is oriented parallel to the silicon crystal { | 02-26-2009 |
20090072290 | SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR - An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode. | 03-19-2009 |
20090072355 | DUAL SHALLOW TRENCH ISOLATION STRUCTURE - A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths. | 03-19-2009 |
20090079027 | SHALLOW TRENCH ISOLATION STRUCTURE COMPATIBLE WITH SOI EMBEDDED DRAM - A deep trench is formed in a semiconductor-on-insulator (SOI) substrate and a pad layer thereupon. A conductive trench fill region is formed in the deep trench. A planarizing material layer having etch selectivity relative to the pad layer is applied. A portion of the pad layer having an edge that is vertically coincident with a sidewall of the deep trench is exposed by lithographic means. Exposed portion of the pad layer are removed selective to the planarizing material layer, followed by removal of exposed portion of a semiconductor layer selective to the conductive trench fill region by an anisotropic etch. The planarizing material layer is removed and a shallow trench isolation structure having a lower sidewall that is self-aligned to an edge of the original deep trench is formed. Another shallow trench isolation structure may be formed outside the deep trench concurrently. | 03-26-2009 |
20090079030 | Forming SOI Trench Memory with Single-Sided Buried Strap - A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench. | 03-26-2009 |
20090101956 | EMBEDDED TRENCH CAPACITOR HAVING A HIGH-K NODE DIELECTRIC AND A METALLIC INNER ELECTRODE - A deep trench is formed in a semiconductor substrate and a pad layer thereupon, and filled with a dummy node dielectric and a dummy trench fill. A shallow trench isolation structure is formed in the semiconductor substrate. A dummy gate structure is formed in a device region after removal of the pad layer. A first dielectric layer is formed over the dummy gate structure and a protruding portion of the dummy trench fill and then planarized. The dummy structures are removed. The deep trench and a cavity formed by removal of the dummy gate structure are filled with a high dielectric constant material layer and a metallic layer, which form a high-k node dielectric and a metallic inner electrode of a deep trench capacitor in the deep trench and a high-k gate dielectric and a metal gate in the device region. | 04-23-2009 |
20090101957 | SIMPLIFIED METHOD OF FABRICATING ISOLATED AND MERGED TRENCH CAPACITORS - Trench capacitors having small and large sizes can be formed simultaneously using a combined lithography process in which openings in a photomask have the same dimensions and spacings. Larger capacitors are formed when the openings in the photomask are aligned with one crystal plane of the semiconductor substrate causing the resulting trenches in the semiconductor substrate to merge. Smaller capacitors are formed when the openings in the photomask are aligned with another crystal plane of the semiconductor substrate in which case each trench remains separate from other trenches. | 04-23-2009 |
20090108315 | TRENCH MEMORY WITH MONOLITHIC CONDUCTING MATERIAL AND METHODS FOR FORMING SAME - A trench memory filled with a monolithic conducting material and methods for forming the same are disclosed. The trench memory includes a trench that has only a single, monolithic conducting material within the trench. The method includes forming a trench with a collar in the trench; forming a node dielectric on a sidewall of the trench; and filling the trench with a monolithic conducting material, such as polysilicon. | 04-30-2009 |
20090176339 | Method of multi-port memory fabrication with parallel connected trench capacitors in a cell - A method is provided for fabricating a multi-port memory in which a plurality of parallel connected capacitors are in a cell. A plurality of trench capacitors are formed which have capacitor dielectric layers extending along walls of the plurality of trenches, the plurality of trench capacitors having first capacitor plates and second capacitor plates opposite the capacitor dielectric layers from the first capacitor plates. The first capacitor plates are conductively tied together and the second capacitor plates are conductively tied together. In this way, the first capacitor plates are adapted to receive a same variable voltage and the second capacitor plates are adapted to receive a same fixed voltage. | 07-09-2009 |
20090242936 | STRAINED ULTRA-THIN SOI TRANSISTOR FORMED BY REPLACEMENT GATE - A semiconductor structure is described. The structure includes a transistor formed in a semiconductor substrate, the semiconductor substrate having a semiconductor-on-insulator (SOI) layer; a channel associated with the transistor and formed on a first portion of the SOI layer; and a source/drain region associated with the transistor and formed in a second portion of the SOI layer and in a recess at each end of the channel, where the second portion of the SOI layer is substantially thicker than the first portion of the SOI layer. A method of fabricating the semiconductor structure is also described. The method includes forming a dummy gate in a semiconductor substrate; performing a SIMOX process to form a SOI layer such that a first portion of the SOI layer under the dummy gate is substantially thinner than a second portion of the SOI layer; forming a source/drain extension in the SOI layer; and recessing the source/drain extension for forming a source/drain region; epitaxially growing the second portion of the SOI layer; forming an insulating layer over the epitaxial growth; removing the dummy gate for forming a gate opening; and filling the gate opening with a gate dielectric material and a gate conductor material. | 10-01-2009 |
20090267186 | SEMICONDUCTOR STRUCTURE INCLUDING TRENCH CAPACITOR AND TRENCH RESISTOR - A structure and a method for fabrication of the structure use a capacitor trench for a trench capacitor and a resistor trench for a trench resistor. The structure is typically a semiconductor structure. In a first instance, the capacitor trench has a linewidth dimension narrower than the resistor trench. The trench linewidth difference provides an efficient method for fabricating the trench capacitor and the trench resistor. In a second instance, the trench resistor comprises a conductor material at a periphery of the resistor trench and a resistor material at a central portion of the resistor trench. | 10-29-2009 |
20090321853 | HIGH-k/METAL GATE MOSFET WITH REDUCED PARASITIC CAPACITANCE - The present invention provides a high-k gate dielectric/metal gate MOSFET that has a reduced parasitic capacitance. The inventive structure includes at least one metal oxide semiconductor field effect transistor (MOSFET) | 12-31-2009 |
20100032742 | INTEGRATED CIRCUITS COMPRISING AN ACTIVE TRANSISTOR ELECTRICALLY CONNECTED TO A TRENCH CAPACITOR BY AN OVERLYING CONTACT AND METHODS OF MAKING - A method of forming an integrated circuit comprises: providing a semiconductor topography comprising an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; forming an interlevel dielectric across the semiconductor topography; concurrently etching (i) a first opening through the interlevel dielectric to the drain junction of the active transistor and the trench capacitor, and (ii) a second opening through the interlevel dielectric to the source junction of the active transistor; and filling the first opening and the second opening with a conductive material to form a strap for electrically connecting the trench capacitor to the drain junction of the active transistor and to also form a contact for electrically connecting the source junction to an overlying level of the integrated circuit. | 02-11-2010 |
20100044794 | ASYMMETRIC MULTI-GATED TRANSISTOR AND METHOD FOR FORMING - In one embodiment, there is an asymmetric multi-gated transistor that has a semiconductor fin with a non-uniform doping profile. A first portion of the fin has a higher doping concentration while a second portion of the fin has a lower doping concentration. In another embodiment, there is an asymmetric multi-gated transistor with gate dielectrics formed on the semiconductor fin that vary in thickness. This asymmetric multi-gated transistor has a thin gate dielectric formed on a first side portion of the semiconductor fin and a thick gate dielectric formed on a second side portion of the fin. | 02-25-2010 |
20100109049 | PATTERNED STRAINED SEMICONDUCTOR SUBSTRATE AND DEVICE - A device that includes a pattern of strained material and relaxed material on a substrate, a strained device in the strained material, and a non-strained device in the relaxed material. The strained material may be silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. Carbon-doped silicon or germanium-doped silicon may be used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon. | 05-06-2010 |
20100252873 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced. | 10-07-2010 |
20110108895 | METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer. | 05-12-2011 |
20120211814 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced. | 08-23-2012 |
20130228840 | EMBEDDED DRAM MEMORY CELL WITH ADDITIONAL PATTERNING LAYER FOR IMPROVED STRAP FORMATION - A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed. | 09-05-2013 |
20140262039 | METHOD OF FORMING ASYMMETRIC SPACERS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING ASYMMETRIC SPACERS - A method of fabricating asymmetrical spacers, structures fabricated using asymmetrical spacers and an apparatus for fabricating asymmetrical spacers. The method includes: forming on a substrate, a structure having a top surface and opposite first and second sidewalls and having a longitudinal axis parallel to the sidewalls; forming a conformal layer on the top surface of the substrate, the top surface of the structure and the sidewalls of the structure; tilting the substrate about a longitudinal axis relative to a flux of reactive ions, the flux of reactive ions striking the conformal layer at acute angle; and exposing the conformal layer to the flux of reactive ions until the conformal layer is removed from the top surface of the structure and the top surface of the substrate leaving a first spacer on the first sidewall and a second spacer on the second sidewall, the first spacer thinner than the second spacer. | 09-18-2014 |