Patent application number | Description | Published |
20120142159 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Methods for fabricating a semiconductor device are provided wherein, in an embodiment, the method includes the steps of forming a gate electrode on a semiconductor substrate, forming a trench by recessing the semiconductor substrate in the vicinity of the gate electrode, doping an anti-diffusion ion into a portion of the semiconductor substrate in the trench, and growing an impurity-doped epitaxial layer on the semiconductor substrate doped with the anti-diffusion ion. | 06-07-2012 |
20120269498 | UNIT FOR SUPPORTING A SUBSTRATE AND APPARATUS FOR TREATING A SUBSTRATE WITH THE UNIT - A substrate treatment apparatus and a supporting unit are provided. The substrate treatment apparatus includes a chamber in which a substrate is processed; a supporting unit that is disposed in the chamber and is configured to support the substrate; and a heating member that is configured to apply heat to the substrate supported by the supporting unit. The supporting unit includes a plate; a plurality of supporting pins upwardly protruding from the plate; and at least one auxiliary pin upwardly protruding from the plate. A distance between a central point of the plate and the at least one auxiliary pin is different from a distance between the central point of the plate and the supporting pins. | 10-25-2012 |
20120299154 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEBICE - A semiconductor device having an improved negative bias temperature instability lifetime characteristic is manufactured by forming a first insulating layer on a substrate, performing a first nitridation on the first insulating layer to form a second insulating layer, and sequentially performing a first and second anneal on the second insulating layer to form a third insulating layer, wherein the second anneal is performed at a higher temperature and with a different gas than the first anneal. A second nitridation is performed on the third insulating layer to form a fourth insulating layer, and a sequential third and fourth anneal on the fourth insulating layer forms a fifth insulating layer. The third anneal is performed at a higher temperature than the first anneal, and the fourth anneal is performed at a higher temperature than the second anneal and with a different gas than the third anneal. | 11-29-2012 |