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Kancherla
Anantha R. Kancherla, Redmond, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20090256849 | Systems and Methods for Providing Intermediate Targets in a Graphics System - Systems and methods for utilizing intermediate target(s) in connection with computer graphics in a computer system are provided. In various embodiments, intermediate memory buffers in video memory are provided and utilized to allow serialized programs from graphics APIs to support algorithms that exceed the instruction limits of procedural shaders for single programs. The intermediate buffers may also allow sharing of data between programs for other purposes as well, and are atomically accessible. The size of the buffers, i.e., the amount of data stored in the intermediate targets, can be variably set for a varying amount of resolution with respect to the graphics data. In this regard, a single program generates intermediate data, which can then be used, and re-used, by an extension of the same program and/or any number of other programs any number of times as may be desired, enabling considerable flexibility and complexity of shading programs, while maintaining the speed of modern graphics chips. | 10-15-2009 |
Anantha Rao Kancherla, Redmond, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20080198169 | SYSTEMS AND METHODS FOR DOWNLOADING ALGORITHMIC ELEMENTS TO A COPROCESSOR AND CORRESPONDING TECHNIQUES - Systems and methods for downloading algorithmic elements to a coprocessor and corresponding processing and communication techniques are provided. For an improved graphics pipeline, the invention provides a class of co-processing device, such as a graphics processor unit (GPU), providing improved capabilities for an abstract or virtual machine for performing graphics calculations and rendering. The invention allows for runtime-predicated flow control of programs downloaded to coprocessors, enables coprocessors to include indexable arrays of on-chip storage elements that are readable and writable during execution of programs, provides native support for textures and texture maps and corresponding operations in a vertex shader, provides frequency division of vertex streams input to a vertex shader with optional support for a stream modulo value, provides a register storage element on a pixel shader and associated interfaces for storage associated with representing the “face” of a pixel, provides vertex shaders and pixel shaders with more on-chip register storage and the ability to receive larger programs than any existing vertex or pixel shaders and provides 32 bit float number support in both vertex and pixel shaders. | 08-21-2008 |
Mani Kancherla, Milpitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100325280 | Load Balance Connections Per Server In Multi-Core/Multi-Blade System - A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade. | 12-23-2010 |
| 20110010481 | MASSIVE MULTI-CORE PROCESSOR BUILT WITH SERIAL SWITCHING - A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards. | 01-13-2011 |
Mani Prasad Kancherla, Santa Clara, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20090276601 | VIRTUAL MEMORY MAPPING FOR EFFICIENT MEMORY USAGE - A processor (e.g. utilizing an operating system and/or circuitry) may access physical memory by paging, where a page is the smallest partition of memory mapped by the processor from a virtual address to a physical address. An application program executing on the processor addresses a virtual address space so that the application program may be unaware of physical memory paging mechanisms. A memory control layer manages physical memory space in units of sub-blocks, wherein a sub-blocks is smaller than a size of the page. Multiple virtual address blocks may be mapped to the same physical page in memory. A sub-block can be moved from a page (e.g. from one physical memory to a second physical memory) without moving other sub-blocks within the page in a manner that is transparent to the application program. | 11-05-2009 |
Mani Prasad Kancherla, Milpitas, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20110126196 | CORE-BASED VISUALIZATION - Techniques for providing core-based virtualization based upon cores provided by one or more processors of a system. A device such as a network device comprising multiple processor cores provides for core-based virtualization. | 05-26-2011 |