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Kanamitsu, JP
Hiromoto Kanamitsu, Funabashi-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110317292 | PIEZOELECTRIC ACTUATOR AND LENS BARREL - A piezoelectric actuator includes: a plurality of first piezoelectric elements; a first member that is interposed between opposing faces of the plurality of the first piezoelectric elements and that is driven in a first direction by the plurality of the first piezoelectric elements; a second piezoelectric element that is disposed in the first member; a second member that is disposed in contact with the second piezoelectric element and that is driven in a second direction intersecting the first direction by the second piezoelectric element; and a third member that comes in contact with the second member and that is moved relative to the first member by driving the second member. | 12-29-2011 |
Kenji Kanamitsu, Hitachinaka JP
| Patent application number | Description | Published |
|---|---|---|
| 20080293230 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A silicon-rich oxide (SRO) film is arranged over an uppermost third-level wiring in a semiconductor device. Then, a silicon oxide film and a silicon nitride film lying over the third-level wiring are dry-etched to expose part of the third-level wiring to thereby form a bonding pad and to form an opening over the fuse. In this procedure, the SRO film serves as an etch stopper. This optimizes the thickness of the dielectric films lying over the fuse. | 11-27-2008 |
| 20090029524 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A TRENCH - A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion. | 01-29-2009 |
Kenji Kanamitsu, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20120017948 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Suppressed is damage of a semiconductor wafer due to charging of a cleaning liquid used in a single wafer type wafer cleaning step. | 01-26-2012 |
Kenji Kanamitsu, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20100019324 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 μm, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi | 01-28-2010 |
| 20110237036 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - By ion-implanting an inert gas, for example, nitrogen into a polycrystalline silicon film in an nMIS forming region from an upper surface of the polycrystalline silicon film down to a predetermined depth, an upper portion of the polycrystalline silicon film is converted to an amorphous form to form an amorphous/polycrystalline silicon film. And then, an n-type impurity, for example, phosphorous is ion-implanted into the amorphous/polycrystalline silicon film to form an n-type amorphous/polycrystalline silicon film, the n-type amorphous/polycrystalline silicon film is processed to form a gate electrode having a gate length shorter than 0.1 μm, a sidewall formed of an insulating film is formed on a side wall of the gate electrode, and a source/drain diffusion layer is formed. Thereafter, a cobalt silicide (CoSi | 09-29-2011 |
Michitaro Kanamitsu, Ome JP
| Patent application number | Description | Published |
|---|---|---|
| 20080266937 | SEMICONDUCTOR DEVICE - A semiconductor device of the present invention has a memory cell array having plural CMOS static memory cells provided at intersecting portions of plural word lines and plural complementary bit lines. In the memory cell array, a switch MOSFET which is in an OFF state in a first operation mode and in an ON state in a second operation mode different from the first operation mode and first-conductivity-type and second-conductivity-type MOSFETs having a diode configuration are provided in parallel between a first source line to which sources of first-conductivity-type MOSFETs constituting first and second CMOS inverter circuits constituting the plural static memory cells are connected and a first power supply line corresponding to the first source line. A second source line to which sources of the second conductivity-type MOSFETs constituting the first and second CMOS inverter circuits are connected is connected to the second power supply line corresponding thereto. | 10-30-2008 |
Norimasa Kanamitsu, Takarazuka-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090170835 | ISOINDOLINE DERIVATIVES - Provided is a novel isoindoline compound of the formula (I): | 07-02-2009 |
Shingo Kanamitsu, Kanagawa-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20100051056 | FOREIGN OBJECT REMOVAL METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A tip of a carbon nanotube is lowered toward a recess where a foreign object exists to cause the tip of the carbon nanotube to contact a bottom face of the recess. Subsequently, the carbon nanotube is further lowered to cause the carbon nanotube to sag, and a side face of the carbon nanotube is pressed against the bottom face of the recess. A force is applied to the foreign object by moving the carbon nanotube on the bottom face of the recess in a state where the side face is pressed against the bottom face of the recess. | 03-04-2010 |
| 20100092876 | METHOD FOR REPAIRING PHOTO MASK, SYSTEM FOR REPAIRING PHOTO MASK AND PROGRAM FOR REPAIRING PHOTO MASK - There is provided a method for repairing a photo mask in this invention, including, obtaining a first image being a photo mask image including a defect area of the photo mask by a repair apparatus, obtaining a second image being a wafer printing image of the photo mask including the defect area by an inspection apparatus, superimposing the first image and the second image to identify a position of the defect area in the first image, and repairing the defect area by the repair apparatus. | 04-15-2010 |
| 20100186768 | FOREIGN MATTER REMOVING METHOD FOR LITHOGRAPHIC PLATE AND METHOD FOR MANUFACTURING LITHOGRAPHIC PLATE - A method for removing foreign matter attached to a photomask, includes: irradiating the foreign matter with an electron beam in an etching gas atmosphere in which the foreign matter or a bottom surface of the photomask is etched by irradiation with the electron beam; or irradiating the foreign matter with the electron beam in a deposition gas atmosphere in which a solid material is generated by irradiation with the electron beam to deposit the solid material on the foreign matter, and applying a force to the solid material with an AFM probe. | 07-29-2010 |
| 20110290134 | IMPRINT MASK, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, an imprint mask includes a quartz plate. The quartz plate has a plurality of concave sections formed in part of an upper surface on the quartz plate, and impurities are contained in a portion between the concave sections in the quartz plate. | 12-01-2011 |
Shingo Kanamitsu, Kawasaki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090098472 | Pattern Evaluation Method - In a pattern evaluation method of determining whether a pattern formed on a photomask is acceptable, an aberration parameter of an image quality evaluation apparatus for determining a pattern image intensity in transferring a pattern formed on a photomask onto a wafer is acquired. An acceptance criterion value used in determining whether an abnormal pattern of the photomask including the effect of aberration of the image quality evaluation apparatus is acceptable is set through a lithographic simulation using the acquired aberration parameter. Then, using the image quality evaluation apparatus, an image intensity of the abnormal pattern of the photomask and an image intensity of a normal pattern corresponding to the abnormal pattern are obtained. It is determined whether the difference between the two acquired image intensities is within the set acceptance criterion value. | 04-16-2009 |
| 20100112464 | DEFECT CORRECTION METHOD FOR EUV MASK - According to an aspect of the present invention, there is provided a method for correcting a defect in an EUV mask, the method including: preparing an EUV mask including an absorption layer and an anti-reflection layer forming a pattern; recognizing a defect region in the pattern; defining a first region and a second region on the defect region, the second region extending from a desired pattern edge by a given distance, the first region being defined on the rest; removing the first region of the anti-reflection layer and the absorption layer by irradiating a beam in a first atmosphere; removing the second region of the anti-reflection layer and the absorption layer by irradiating the beam in a second atmosphere; and oxidizing an exposed side surface of the desired pattern edge of the absorption layer. | 05-06-2010 |
Yasuji Kanamitsu, Nara JP
| Patent application number | Description | Published |
|---|---|---|
| 20100080979 | POLYPROPYLENE RESIN COMPOSITION EXPANSION-MOLDED ARTICLE USING THE RESIN COMPOSITION, AND PROCESS FOR PRODUCTION OF THE EXPANSION-MOLDED ARTICLE - [Problems] To provide: a polypropylene resin composition which can produce an expansion-molded article showing excellent low-temperature impact properties even when expanded at an increased expansion rate; an expansion-molded article using the polypropylene resin composition, which has excellent low-temperature impact properties, is light in weight, and has good appearance; and a process for producing the expansion-molded article. | 04-01-2010 |