Patent application number | Description | Published |
20080222579 | Moment-Based Method and System for Evaluation of Metal Layer Transient Currents in an Integrated Circuit - A moment-based method and system for evaluation of metal layer transient currents in an integrated circuit provides a computationally efficient evaluation of transient current magnitudes through each interconnect in the metal layer. The determinable magnitudes include peak, rms and average current, which can be used in subsequent reliability analyses. Interconnect path nodes are traversed and circuit moments are either retrieved from a previous interconnect delay analysis or are computed. For each pair of nodes, current moments are computed from the circuit moments. The average current is computed from the zero-order circuit moment and the peak and rms currents are obtained from expressions according to a lognormal or other distribution shape assumption for the current waveform at each node. | 09-11-2008 |
20080255792 | TEST SYSTEM AND COMPUTER PROGRAM FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY - A test system and computer program for measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The test system and computer program control a characterization array circuit that imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically. | 10-16-2008 |
20080258750 | METHOD FOR DETERMINING THRESHOLD VOLTAGE VARIATION USING A DEVICE ARRAY - A method of measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The characterization array imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically. | 10-23-2008 |
20080258752 | METHOD AND APPARATUS FOR MEASURING DEVICE MISMATCHES - A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements. | 10-23-2008 |
20080278182 | Test Structure for Statistical Characterization of Metal and Contact/Via Resistances - A test structure for measuring resistances of a large number of interconnect elements such as metal, contacts and vias includes an array of test cells in rows and columns. Power is selectively supplied to test cells in a given column while current is selectively steered from test cells in a given row. A first voltage near the power input node of a device under test (DUT) is selectively sensed, and a second voltage near the current measurement tap is selectively sensed. The resistance of the DUT is the difference of the first and second voltages divided by the current. Additional voltage taps are provided for test cells having multiple resistive elements. This array of test cells can be used to characterize the statistical distribution of resistance variation and to identify physical location of defects in resistive elements. | 11-13-2008 |
20080284460 | METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION - A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures. | 11-20-2008 |
20080294410 | METHOD OF SEPARATING THE PROCESS VARIATION IN THRESHOLD VOLTAGE AND EFFECTIVE CHANNEL LENGTH BY ELECTRICAL MEASUREMENTS - A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient λ relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient λ times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff. | 11-27-2008 |
20090102508 | Pulsed Dynamic Logic Environment Metric Measurement Circuit - A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the dynamic logic stages is sensitive. The number of dynamic logic stages that evaluate within a given pulse provides a direct measure of the pulse width, and thus the value of the circuit metric. The pulse may be generated from a logical exclusive-OR combination of a clock signal provided from two circuit paths that differ in sensitivity to the environment metric to be measured. One circuit path may have a delay substantially determined only by wire delay, which is not substantially sensitive to circuit environment metrics such as power supply voltage. | 04-23-2009 |
20090125258 | SCANNABLE VIRTUAL RAIL RING OSCILLATOR CIRCUIT AND SYSTEM FOR MEASURING VARIATIONS IN DEVICE CHARACTERISTICS - A scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors. | 05-14-2009 |
20090138227 | Characterizing Across-Die Process Variation - Measurement of individual quiescent supply currents from multiple power supply pads located across a semiconductor die provides a means of characterizing across-die variation. A ratio is created by combining the individual pad supply current with the sum of all pad supply currents for a given die. An n-tuple is formed from the set of ratios for all pad supply currents to provide a unique signature for different across-die variation profiles. | 05-28-2009 |
20090160463 | CHARACTERIZATION CIRCUIT FOR FAST DETERMINATION OF DEVICE CAPACITANCE VARIATION - A test circuit for fast determination of device capacitance variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter. | 06-25-2009 |
20090160477 | METHOD AND TEST SYSTEM FOR FAST DETERMINATION OF PARAMETER VARIATION STATISTICS - A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter. | 06-25-2009 |
20090251167 | Array-Based Early Threshold Voltage Recovery Characterization Measurement - A method and test circuit provide measurements to aid in the understanding of time-varying threshold voltage changes such as negative bias temperature instability and positive bias temperature instability. In order to provide accurate measurements during an early stage in the threshold variation, a current generating circuit is integrated on a substrate with the device under test, which may be a device selected from among an array of devices. The current generating circuit may be a current mirror that responds to an externally-supplied current provided by a test system. A voltage source circuit may be included to hold the drain-source voltage of the transistor constant, although not required. A stress is applied prior to the measurement phase, which may include a controllable relaxation period after the stress is removed. | 10-08-2009 |
20100074040 | Method and Apparatus for Measuring Statistics of Dram Parameters with Minimum Perturbation to Cell Layout and Environment - The present invention provides a method for measuring statistics of dynamic random access memory (DRAM) process parameters for improving yield and performance of a DRAM. The basic principles for measuring capacitance are similar to charge based capacitance (CBCM), however the present invention differs in several fundamental aspects. In one embodiment, the method includes receiving a selection of a storage cell of the DRAM; measuring a storage cell capacitance (C | 03-25-2010 |
20100122231 | ELECTRICALLY-DRIVEN OPTICAL PROXIMITY CORRECTION TO COMPENSATE FOR NON-OPTICAL EFFECTS - A contour of a mask design for an integrated circuit is modified to compensate for systematic variations arising from non-optical effects such as stress, well proximity, rapid thermal anneal, or spacer thickness. Electrical characteristics of a simulated integrated circuit chip fabricated using the mask design are extracted and compared to design specifications, and one or more edges of the contour are adjusted to reduce the systematic variation until the electrical characteristic is within specification. The particular electrical characteristic preferably depends on which layer is to be fabricated from the mask: on-current for a polysilicon; resistance for contact; resistance and capacitance for metal; current for active; and resistance for vias. For systematic threshold voltage variation, the contour is adjusted to match a gate length which corresponds to an on-current value according to pre-calculated curves for contour current and gate length at a nominal threshold voltage of the chip. | 05-13-2010 |
20100225348 | METHOD AND APPARATUS FOR STATISTICAL CMOS DEVICE CHARACTERIZATION - A unified test structure having a large number of electronic devices under test is used to characterize both capacitance-voltage parameters (C-V) and current-voltage parameters (I-V) of the devices. The devices are arranged in an array of columns and rows, and selected by control logic which gates input/output pins that act variously as current sources, sinks, clamps, measurement ports and sense lines. The capacitance-voltage parameter is measured by taking baseline and excited current measurements for different excitation voltage frequencies, calculating current differences between the baseline and excited current measurements, and generating a linear relationship between the current differences and the different frequencies. The capacitance is then derived by dividing a slope of a line representing the linear relationship by the excitation voltage. Different electronic devices may be so tested, including transistors and interconnect structures. | 09-09-2010 |
20100262412 | INTEGRATED CIRCUIT MODELING BASED ON EMPIRICAL TEST DATA - In accordance with one embodiment, a plurality of empirical measurements of a fabricated integrated circuit including a fabricated transistor having multiple terminals is received. The plurality of empirical measurements each include an empirical terminal current set and an empirical terminal voltage set for the terminals of the fabricated transistor. A mathematical simulation model of a simulated transistor is also received. Utilizing the mathematical simulation model, an intermediate data set is calculated by determining, for each of a plurality of different terminal voltage sets, a simulated terminal current set and a simulated terminal charge set. A modeling tool processes the intermediate data set to obtain a time domain simulation model of the fabricated transistor that, for each of the plurality of empirical measurements, provides a simulated terminal charge set. The time domain simulation model is stored in a computer-readable data storage medium. | 10-14-2010 |
20100262413 | COMPENSATING FOR VARIATIONS IN DEVICE CHARACTERISTICS IN INTEGRATED CIRCUIT SIMULATION - According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium. | 10-14-2010 |
20100318313 | MEASUREMENT METHODOLOGY AND ARRAY STRUCTURE FOR STATISTICAL STRESS AND TEST OF RELIABILTY STRUCTURES - System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms. | 12-16-2010 |
20100321042 | CONFIGURABLE PSRO STRUCTURE FOR MEASURING FREQUENCY DEPENDENT CAPACITIVE LOADS - A configurable PSRO measurement circuit is used to measure the frequency dependent capacitance of a target through silicon via (TSV) or other conductive structure. Measurements of the target structure are aided by using adjustable resistors and a de-embedding structure to measure the effects of parasitic capacitance, C | 12-23-2010 |
20100327892 | Parallel Array Architecture for Constant Current Electro-Migration Stress Testing - A parallel array architecture for constant current electro-migration stress testing is provided. The parallel array architecture comprises a device under test (DUT) array having a plurality of DUTs coupled in parallel and a plurality of localized heating elements associated with respective ones of the DUTs in the DUT array. The architecture further comprises DUT selection logic that isolates individual DUTs within the array. Moreover, the architecture comprises current source logic that provides a reference current and controls the current through the DUTs in the DUT array such that each DUT in the DUT array has substantially a same current density, and current source enable logic for selectively enabling portions for the current source logic. Electro-migration stress testing is performed on the DUTs of the DUT array using the heating elements, the DUT selection logic, current source logic, and current source enable logic. | 12-30-2010 |
20100333049 | Model-Based Retargeting of Layout Patterns for Sub-Wavelength Photolithography - Mechanism are provided for model-based retargeting of photolithographic layouts. An optical proximity correction is performed on a set of target patterns for a predetermined number of iterations until a counter value exceeds a maximum predetermined number of iterations in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes in response to the counter value exceeding the maximum predetermined number of iterations. A normalized image log slope (NILS) extraction is performed on the set of target shapes and use the set of lithographic contours to produce NILS values. The set of target patterns is modified based on the NILS values in response to the NILS values failing to be within a predetermined limit. The steps are repeated until the NILS values are within the predetermined limit. | 12-30-2010 |
20110119642 | Simultaneous Photolithographic Mask and Target Optimization - A mechanism is provided for simultaneous photolithographic mask and target optimization (SMATO). A lithographic simulator generates an image of a mask shape on a wafer thereby forming one or more lithographic contours. A mask and target movement module analytically evaluates a direction for mask and target movement thereby forming a plurality of pairs of mask and target movements. The mask and target movement module identifies a best pair of mask and target movements from the plurality of mask and target movements that minimizes a weighted cost function. A shape adjustment module adjusts at least one of a target shape or the mask shape based on the best pair of mask and target movements. | 05-19-2011 |
20110138342 | Retargeting for Electrical Yield Enhancement - A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting. | 06-09-2011 |
20110150343 | Optical Proximity Correction for Transistors Using Harmonic Mean of Gate Length - A mechanism is provided for harmonic mean optical proximity correction (HMOPC). A lithographic simulator in a HMOPC mechanism generates an image of a mask shape based on a target shape on a wafer thereby forming one or more lithographic contours. A cost function evaluator module determines a geometric cost function associated with the one or more lithographic contours. An edge movement module minimizes the geometric cost function thereby forming a minimized geometric cost function. The edge movement module determines a set of edge movements for each slice in a set of slices associated with the one or more lithographic contours using the minimized geometric cost function. The edge movement module moves the edges of the mask shape using the set of edge movements for each slice in the set of slices. The HMOPC mechanism then produces a clean mask shape using the set of edge movements. | 06-23-2011 |
20110154271 | Optical Proximity Correction for Improved Electrical Characteristics - A method, computer program product, and data processing system for performing an improved optical proximity correction are disclosed, which better respect the electrical properties of the device being manufactured. A preferred embodiment of the present invention performs OPC by first dividing the perimeter of a mask region into a plurality of segments, then grouping the segments into at least two distinct groups, wherein segments in the first of these groups are adjusted in position so as to minimize edge placement error (EPE) when the photolithography using the mask is simulated. Segments in the second group are adjusted in position so as to minimize cumulative error in a dimension spanning the region, wherein the span of such dimension extends from segments in the first group to segments in the second group. Correction so obtained by this process more readily preserves the intended electrical behavior of the original device design. | 06-23-2011 |
20110283251 | Effective Gate Length Circuit Modeling Based On Concurrent Length And Mobility Analysis - Disclosed is a computer implemented method and computer program product to determine metal oxide semiconductor (MOS) gate functional limitations. A simulator obtains a plurality of slices of a MOS gate, the slices each comprising at least one parameter, the parameter comprising a slice gate width and a slice gate length. The simulator determines a current for each slice based on a slice gate length of the slice to form a length-based current for each slice. The simulator determines a length-based current for the MOS gate by summing the length-based current for each slice. The simulator calculates a stress profile for each slice. The simulator determines a slice carrier mobility for each slice based on the stress profile of each slice. The simulator determines a carrier mobility-based current for each slice, based on each slice carrier mobility. The simulator determines a carrier mobility for the MOS gate based on the carrier mobility-based current for each slice. The simulator determines an effective length for the MOS gate based on the length-based current. | 11-17-2011 |
20120040280 | Simultaneous Optical Proximity Correction and Decomposition for Double Exposure Lithography - A mechanism is provided for simultaneous optical proximity correction (OPC) and decomposition for double exposure lithography. The mechanism begins with two masks that are equal to each other and to the target. The mechanism simultaneously optimizes both masks to obtain a wafer image that both matches the target and is robust to process variations. The mechanism develops a lithographic cost function that optimizes for contour fidelity as well as robustness to variation. The mechanism minimizes the cost function using gradient descent. The gradient descent works on analytically evaluating the derivative of the cost function with respect to mask movement for both masks. It then moves the masks by a fraction of the derivative. | 02-16-2012 |
20120110521 | Split-Layer Design for Double Patterning Lithography - A mechanism is provided for converting a set of single-layer design rules into a set of split-layer design rules for double patterning lithography (DPL). The set of single-layer design rules and minimum lithographic resolution pitch constraints for single exposure are identified. The set of single-layer design rules comprise a first plurality of minimum distances that are required by a set of first shapes in a single-layer design. Each of the first plurality of minimum distances in the set of single-layer design rules are modified with regard to the minimum lithographic resolution pitch constraints for single exposure, thereby forming the set of split-layer design rules. The set of split-layer design rules comprise a second plurality of minimum distances that are required by a set of second shapes and a set of third shapes in a split-layer design. The set of split-layer design rules are then coded into a design rule checker. | 05-03-2012 |
20120260223 | Retargeting for Electrical Yield Enhancement - A mechanism is provided for electrical yield enhancement retargeting of photolithographic layouts. Optical proximity correction is performed on a set of target patterns in order to produce a set of optical proximity correction mask shapes. A set of lithographic contours is generated for each of the set of optical proximity correction mask shapes. A determination is made of electrical yield sensitivities for at least one shape in a set of shapes in the set of target patterns. A determination is also made as to an amount and a direction of retargeting for each of the at least one shape in the set of shapes based on the electrical yield sensitivity of the shape. A new set of target patterns with retargeted edges is generated for each shape in the at least one shape based on the amount and the direction of retargeting. | 10-11-2012 |
20120317523 | Reducing Through Process Delay Variation in Metal Wires - A mechanism is provided for reducing through process delay variation in metal wires by layout retargeting. The mechanism performs initial retargeting, decomposition, and resolution enhancement techniques. For example, the mechanism may perform optical proximity correction. The mechanism then performs lithographic simulation and optical rules checking. The mechanism provides retargeting rules developed based on coupling lithography simulation and resistance/capacitance (RC) extraction. The mechanism performs RC extraction to capture non-linear dependency of RC on design shape dimensions. If the electrical properties in the lithographic simulation are within predefined specifications, the mechanism accepts the retargeting rules; however, if the electrical properties from RC extraction are outside the predefined specifications, the mechanism modifies the retargeting rules and repeats resolution enhancement techniques. | 12-13-2012 |
20120317529 | Rapid Estimation of Temperature Rise in Wires Due to Joule Heating - A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations. | 12-13-2012 |
20130003108 | Frequency Domain Layout Decomposition in Double Patterning Lithography - A mechanism is provided for frequency domain layout decomposition in double pattern lithography (DPL) based on Fourier coefficient optimization (FCO). The Fourier transform of a layout represents the spatial frequency terms present in the layout. The mechanism models decomposed patterns for two exposures as a function of the corresponding Fourier coefficients. For each exposure, the mechanism sets the corresponding Fourier coefficients to zero for spatial frequency terms greater than the cut-off frequency of the optical system. The mechanism then optimizes non-zero Fourier coefficients for the two exposures to decompose the original target. The mechanism provides frequency domain optimization instead of conventional spatial domain methods, which naturally leads to optics-aware decomposition and stitch insertion in arbitrary two dimensional patterns. | 01-03-2013 |
20130007674 | RESOLVING DOUBLE PATTERNING CONFLICTS - A mechanism is provided for resolving patterning conflicts. The mechanism performs decomposition with stitches at all candidate locations to find the solution with the minimum number of conflicts. The mechanism then defines interactions between a layout of a first mask and a layout of a second mask through design rules, as well as interactions of mask | 01-03-2013 |
20130061183 | Multiple Patterning Layout Decomposition for Ease of Conflict Removal - A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction, The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features, The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors. | 03-07-2013 |
20130061185 | MASK ASSIGNMENT FOR MULTIPLE PATTERNING LITHOGRAPHY - A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color. | 03-07-2013 |
20130147644 | High Bandwidth Decompression of Variable Length Encoded Data Streams - Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data. | 06-13-2013 |
20130148745 | High Bandwidth Decompression of Variable Length Encoded Data Streams - Mechanisms are provided for decoding a variable length encoded data stream. A decoder of a data processing system receives an input line of data. The input line of data is a portion of the variable length encoded data stream. The decoder determines an amount of bit spill over of the input line of data onto a next input line of data. The decoder aligns the input line of data to begin at a symbol boundary based on the determined amount of bit spill over. The decoder tokenizes the aligned input line of data to generate a set of tokens. Each token corresponds to an encoded symbol in the aligned next input line of data. The decoder generates an output word of data based on the set of tokens. The output word of data corresponds to a word of data in the original set of data. | 06-13-2013 |
20130297292 | High Bandwidth Parsing of Data Encoding Languages - A mechanism is provided for accelerating data exchange language parsing. An input data stream is loaded into a first in, first out (FIFO) memory. A tokenization bit corresponding to a next byte to be read is extracted from a FIFO. A determination is made as to whether the tokenization bit corresponding to the next byte to be read from the FIFO indicates a control character or a non-control character located in an associated FIFO memory location in the FIFO. Responsive to the tokenization bit indicating the control character, the control character that causes a state change in a state machine is processed. Responsive to the tokenization bit indicating the non-control character, a length associated with the tokenized bit is identified and a set of non-control characters that do not cause a state change in the state machine are processed based on the length associated with the tokenized bit. | 11-07-2013 |
20130332146 | High Speed Large Scale Dictionary Matching - A mechanism is provided for dictionary matching. The mechanism loads a plurality of dictionary memory arrays with a set of dictionary words and updates a plurality of status arrays. Each status array of the plurality of status arrays corresponds to a respective one of the plurality of dictionary memory arrays. Each entry of a given status array stores a status bit, which indicates whether a corresponding entry of the corresponding dictionary memory array stores a valid dictionary word. The mechanism receives an input data word and generates a hash value based on the input data word. The mechanism reads a dictionary word from each of the dictionary memory arrays and a status bit from each of the status arrays using the hash value as a read address. The mechanism determines whether a dictionary memory array within the plurality of dictionary memory arrays stores a valid dictionary word that matches the input data word. | 12-12-2013 |
20140049410 | SELECTIVE RECOMPRESSION OF A STRING COMPRESSED BY A PLURALITY OF DIVERSE LOSSLESS COMPRESSION TECHNIQUES - In response to receiving an input string to be compressed, a plurality of diverse lossless compression techniques are applied to the input string to obtain a plurality of compressed strings. The plurality of diverse lossless compression techniques include a template-based compression technique and a non-template-based compression technique. A most compressed string among the plurality of compressed strings is selected. A determination is made regarding whether or not the most compressed string was obtained by application of the template-based compression technique. In response to determining that the most compressed string was obtained by application of the template-based compression technique, the most compressed string is compressed utilizing the non-template-based compression technique to obtain an output string and outputting the output string. In response to determining that the most compressed string was not obtained by application of the template-based compression technique, the most compressed string is output as the output string. | 02-20-2014 |
20140049412 | DATA COMPRESSION UTILIZING LONGEST COMMON SUBSEQUENCE TEMPLATE - In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output. | 02-20-2014 |
20140049413 | DATA COMPRESSION UTILIZING LONGEST COMMON SUBSEQUENCE TEMPLATE - In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output. | 02-20-2014 |
20140065728 | METHOD FOR POST DECOMPOSITION DENSITY BALANCING IN INTEGRATED CIRCUIT LAYOUTS, RELATED SYSTEM AND PROGRAM PRODUCT - Embodiments of the invention provide a method of modifying a decomposed integrated circuit (IC) layout. The method includes providing a decomposed IC layout, the decomposed IC layout including a set of colors; determining a density of each color in the decomposed IC layout, wherein each color includes a plurality of features formed by a related exposure; separating the decomposed IC layout into a set of tiles; determining a first color with a minimum density in one tile of the set of tiles and a second color with a maximum density in tile, the first color including a first set of first features and the second color including a first set of second features; and replacing the first set of second features on the tile with a second set of first features, and the first set of first features on the tile with a second set of second features. | 03-06-2014 |
20140068529 | SOLUTIONS FOR RETARGETING INTEGRATED CIRCUIT LAYOUTS BASED ON DIFFRACTION PATTERN ANALYSIS - A computer-implemented method for retargeting an Integrated Circuit (IC) layout is disclosed. In one embodiment, the method includes generating a diffraction pattern for the IC layout including a set of diffraction-orders, the IC layout including a set of features defined by a set of target edges, analyzing the diffraction pattern with a merit function to estimate printability of the IC layout, monitoring a change in value of the merit function as a position of at least one of the set of target edges is adjusted across a range, and retargeting the set of target edges based on the monitoring of the merit function. | 03-06-2014 |
20140365571 | Automatically Determining Veracity of Documents Posted in a Public Forum - An approach is provided to determine the veracity of an online posting. In the approach, when a posting is received at a web site, a topic for the posting is automatically identified. The approach further identifies actions and corresponding action originators that have been taken to the posting, with the actions being events such as commenting, liking, disliking, re-sharing, posting the online posting. Veracity information is collected about the action originators. A veracity weighting for the action originators is assigned based on the collected veracity information. The actions are analyzed using the veracity weighting to form a weighted veracity summary which is provided to a viewer of the online posting | 12-11-2014 |
20150066878 | Efficient Context Save/Restore During Hardware Decompression of DEFLATE Encoded Data - An approach is provided in which a hardware accelerator receives a request to decompress a data stream that includes multiple deflate blocks and multiple deflate elements compressed according to block-specific compression configuration information. The hardware accelerator identifies a commit point that is based upon an interruption of a first decompression session of the data stream and corresponds to one of the deflate blocks. As such, the hardware accelerator configures a decompression engine based upon the corresponding deflate block's configuration information and, in turn, recommences decompression of the data stream at an input bit location corresponding to the commit point. | 03-05-2015 |
20150085694 | Port Mirroring for Sampling Measurement of Network Flows - Mechanisms are provided for analyzing data traffic through a network. The mechanisms sample data packets of a data flow through a normal port of a network forwarding device of the network. The sampling is performed at least by configuring the network forwarding device to implement port mirroring of the normal port to a designated mirror port of the network forwarding device. The mechanisms forward sampled data packets, copied to the mirror port by virtue of the port mirroring, to a collector computing device. The mechanisms process, by the collector computing device, the sampled data packets to analyze the data flow through the normal port of the network forwarding device. The mechanisms perform, by the collector computing device, an operation based on results of the analysis. | 03-26-2015 |
20150089032 | Scalable Network Configuration with Consistent Updates in Software Defined Networks - Mechanisms are provided for configuring a data flow between a source device and a destination device in a network. The mechanisms receive, from a network control application, a request to establish a network configuration corresponding to a data flow between the source device and the destination device. The request comprises a fine grained header field tuple for defining the data flow. The mechanisms allocate, from a shadow address pool, a shadow address to be mapped to the fine grained header field tuple. The shadow address pool comprises addresses not being used by devices coupled to the network. The mechanisms configure a network infrastructure of the network to route data packets of the data flow from the source device to the destination device based on the shadow address. | 03-26-2015 |
20150089045 | Determining Sampling Rate from Randomly Sampled Events - Mechanisms are provided for determining an event rate. The mechanisms sample a sequence of events to generate a set of sampled events. At least a subset of the sampled events have associated event sequence values indicating a position of the sampled event within the sequence of events. The mechanisms group the sampled events into a plurality of event groups based on a common characteristic of the events. The mechanisms determine, for each event group, sequence values of sampled events associated with the event group. The mechanisms calculate, for each event group, an estimated event rate based on the sequence values of the sampled events associated with the event group and the total number of events in the sequence of events. | 03-26-2015 |
20150089457 | Hierarchical Approach to Triple Patterning Decomposition - A mechanism is provided in a data processing system for hierarchical triple patterning decomposition. The mechanism receives an integrated circuit design. The mechanism enforces boundary conditions on three-color mapping of shapes in a layer of the integrated circuit design at the cell level. The mechanism places cells in the layer of the integrated circuit design. The mechanism identifies post placement coloring conflicts and resolves the post placement coloring conflicts with two-color flipping in coloring runs containing one or more conflicts. | 03-26-2015 |