| Patent application number | Description | Published |
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| 20090289601 | METHOD AND APPARATUS FOR SYSTEM ACQUISITION WHILE MAINTAINING A DEFINED BATTERY LIFE SPAN - A method and an apparatus for system acquisition at a wireless device while maintaining a predetermined battery life span, include determining a level of remaining battery power upon entering an out of service state. A duty cycle, comprising a search time and sleep time, of acquisition attempts is determined such that the level of remaining battery power lasts for the defined battery life span. The duty cycle is determined by adjusting at least one of the search time and the sleep time, depending on how long the remaining battery power is required to last. | 11-26-2009 |
| 20100105373 | Location Information For Control of Mode/Technology - A multimode wireless communication device utilizes location information provided by a co-located autonomous position location receiver to determine a preferred provider database and associated operating mode and operating technology when an out-of-service condition is encountered. The multimode wireless communication device can utilize active preferred provider database while in service and while acquired within a network. The multimode wireless communication device can initiate location-based mode and technology control when in an out-of-service condition. The multimode wireless communication device determines its location and based on the location, accesses a database to determine a preferred provider database. The preferred provider database provides a hierarchical list of available systems and associated information for acquiring and registering with the systems. The multimode wireless communication device reduces a search time and associated power consumption using location-based mode and technology control. | 04-29-2010 |
| 20100322126 | APPARATUS AND METHODS FOR LOW POWER SENSING OF COMMUNICATION ACCESS TECHNOLOGIES - Apparatus and methods for low power sensing of wireless access technologies are disclosed. In particular, a mobile wireless device, such as an access terminal, may utilize a lower power circuitry portion that operates at a lower power than active circuitry, such as a primary transceiver. The lower power circuitry portion includes a configurable searcher that is capable of sensing if signals of one or more various wireless access technologies are present. When the wireless device utilizes sleep or idle modes for power savings, use of the lower power sensing circuitry to sense the presence of wireless access technologies, rather than using an awoken higher power primary transceiver for sensing, affords increased power savings. An added ability of the lower power circuitry to be put into sleep or idles modes achieves even greater power savings. | 12-23-2010 |
| 20110096697 | Automatic Selection of Geographic Area Specific Behavior - A wireless communication device configured for automatic selection of geographic specific behavior is described. The circuitry is configured to receive a message with system information from the network that is mandatorily sent from a base station. The circuitry is also configured to determine the geographic area from the system information using a lookup table. | 04-28-2011 |
| Patent application number | Description | Published |
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| 20090138628 | MULTI-BUS ARCHITECTURE FOR MASS STORAGE SYSTEM-ON-CHIP CONTROLLERS - Systems and methods that can facilitate an expedient and efficient transfer of data between memory components (e.g., flash memory) and host components (e.g., multimedia cards, secure digital cards, etc.) are presented. A memory controller component can be employed to facilitate transferring between the memory components and host components by utilizing a multi-bus architecture. A controller first bus can be utilized for code that can be executed by a controller processor while a controller second bus can be designated for the transfer of data to the mass storage devices. By architecting the memory controller component with two buses, this innovation can provide a higher data throughput than conventional memory controllers. | 05-28-2009 |
| 20090144045 | DATA TRANSMISSION SYSTEM-ON-CHIP MEMORY MODEL BASED VALIDATION - Systems and/or methods that facilitate simulation, verification, and optimization of a data transmission system by utilizing simulation memory component(s) are presented. A simulation memory component can be used to replace memory components and/or hardware components to facilitate early simulation and/or verification of the overall interconnectivity of the system. A simulation memory component(s) can be configured to emulate various sizes of memory components associated with the system. Data throughput can be measured during simulation, and the depth and/or width associated with a simulation memory component can be adjusted to facilitate obtaining a desired data throughput based in part on predefined data throughput criteria. | 06-04-2009 |
| 20090164704 | HIGH PERFORMANCE FLASH CHANNEL INTERFACE - Systems and/or methods that facilitate high performance flash channel interface techniques are presented. Integrated error correction code (ECC) engine and buffer sets facilitate bypassing error correction of data being written to or read from memory, such as flash memory, in addition to single ECC mode or multiple ECC mode. The integrated ECC engines and buffers can quickly analyze data, and provide error correction information or correct error, significantly increasing throughput. In addition, the programmable flash channel interface can provide more rapid development of flash products by accommodating both Open NAND Flash Interface (ONFI) standard flash and legacy flash devices, by using a configurable micro-code engine in the flash interface. | 06-25-2009 |
