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Kamigaki, JP
Kousei Kamigaki, Kagoshima JP
| Patent application number | Description | Published |
|---|---|---|
| 20090207556 | DIELECTRIC CERAMIC AND CAPACITOR - The invention relates to a ceramic dielectric material and to capacitors including the ceramic dielectric material. The ceramic dielectric material of the invention exhibits a high relative dielectric constant and a stable temperature characteristic of the relative dielectric constant. | 08-20-2009 |
Mamoru Kamigaki, Hiroshima-Ken JP
| Patent application number | Description | Published |
|---|---|---|
| 20120064449 | BLACK MAGNETIC IRON OXIDE PARTICLES - The present invention relates to black magnetic iron oxide particles comprising magnetite as a main component, wherein when the black magnetic iron oxide particles are molded into a tablet shape, an electric resistance value of the tablet in an alternating current electric field is controlled to produce an impedance of not less than 2×10 | 03-15-2012 |
Mamoru Kamigaki, Hatsukaichi-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20090007821 | Functional material, dispersion containing the functional material, and process for producing the functional material - A functional material comprising fine coloring particles having an average primary particle diameter of 1 to 50 nm in a dried state, and having a BET specific surface area value of to 500 m | 01-08-2009 |
Mamoru Kamigaki, Otake-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20080206566 | Black magnetic iron oxide particles - The present invention relates to a black magnetic iron oxide particles each having a polyhedral shape wherein when a percentage of dissolution of iron element based on a total amount of iron element contained in the black magnetic iron oxide particles is 50%, a percentage of dissolution of sulfur element based on a total amount of sulfur element contained in the black magnetic iron oxide particles is less than 40%. | 08-28-2008 |
Tetsuya Kamigaki, Yokohama-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20110006424 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes forming a plurality of dummy line patterns arranged at a first pitch on an underlying region, forming first mask patterns having predetermined mask portions formed on long sides of the dummy line patterns, each of the first mask patterns having a closed-loop shape and surrounding each of the dummy line patterns, removing the dummy line patterns, forming a second mask pattern having a first pattern portion which covers end portions of the first mask patterns and inter-end portions each located between adjacent ones of the end portions, etching the underlying region using the first mask patterns and the second mask pattern as a mask to form trenches each located between adjacent ones of the predetermined mask portions, and filling the trenches with a predetermined material. | 01-13-2011 |
Toshio Kamigaki, Toyohashi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100243867 | MAPPING MECHANISM, FOUP AND LOAD PORT - Disclosed herein is a mapping mechanism for carrying out mapping for a FOUP which includes a wafer receiving section on which a plurality of wafers can be placed at a plurality of stages in a heightwise direction and a lid member mounted for opening and closing movement, including: a light emitting member and a light receiving member provided outside the FOUP; and a window member provided on a light path between the light emitting member and the light receiving member which can cross at least part of the wafers placed on the stage portions of the wafer receiving section; the light being caused to pass over all of the stages of the wafer receiving section of the FOUP to carry out the mapping for the FOUP. | 09-30-2010 |
Yoshiaki Kamigaki, Tokorozawa-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20080254582 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING SINGLE-ELEMENT TYPE NON-VOLATILE MEMORY ELEMENTS - A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits. | 10-16-2008 |
Yoshiaki Kamigaki, Takamatsu JP
| Patent application number | Description | Published |
|---|---|---|
| 20090010072 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 01-08-2009 |
| 20100157689 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 06-24-2010 |
| 20110309428 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 12-22-2011 |