# Kameran Azadet, Morganville US

## Kameran Azadet, Morganville, NJ US

Patent application number | Description | Published |
---|---|---|

20090083352 | METHODS AND APPARATUS FOR PERFORMING REDUCED COMPLEXITY DISCRETE FOURIER TRANSFORMS USING INTERPOLATION - Methods and apparatus arc provided for performing reduced complexity discrete Fourier transforms using interpolation An input sequence of length N is transformed by extending the input sequence to an extended input sequence of length M, where M is greater than N (a power of two greater than N); performing a discrete Fourier Transform (DFT), such as a power-of-two DFT, on the extended input sequence to obtain an interpolated sequence; and applying a conversion matrix to the interpolated sequence to obtain a DFT output for the input sequence of length N. The input sequence of length N can be extended to an extended input sequence of length M, for example, by employing a zero padding technique, a cyclic extension technique, a windowing of a cyclic extended sequence technique or a resampling-based interpolation technique to extend the input sequence The conversion matrix is substantially a spar se matrix. | 03-26-2009 |

20090129519 | METHOD AND APPARATUS FOR JOINT EQUALIZATION AND DECODING OF MULTILEVEL CODES - A method and apparatus are disclosed for joint equalization and decoding of multilevel codes, such as the MLT-3 code, which are transmitted over dispersive channels. The MLT-3 code is treated as a code generated by a finite-state machine using a trellis having state dependencies between the various states. A super trellis concatenates the MLT-3 trellis with a trellis representation of the channel. Joint equalization and decoding of the received signal can be performed using the super trellis. A sequence detector is disclosed that uses the super trellis or a corresponding reduced-state trellis to perform joint equalization and decoding of the received signal to decode the MLT-3 coded data bits. The sequence detector may be embodied using maximum likelihood sequence estimation that applies the optimum Viterbi algorithm or a reduced complexity sequence estimation method, such as the reduced-state sequence estimation (RSSE) algorithm. | 05-21-2009 |

20100034333 | Methods And Apparatus For Improved Phase Linearity In A Multi-Phase Based Clock/Timing Recovery System - Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements. | 02-11-2010 |

20100138463 | Digital Signal Processor Having Instruction Set With One Or More Non-Linear Functions Using Reduced Look-Up Table - A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values for the non-linear function that are near the value, x, from at least one look-up table, wherein the at least one look-up table stores a subset of values for the non-linear function; and interpolating the two or more obtained values to obtain a result, y. The interpolation may comprise, for example, a linear interpolation or a polynomial interpolation. In a further variation, a modulo arithmetic operation can be employed for a periodic non-linear function. | 06-03-2010 |

20100138464 | Digital Signal Processor Having Instruction Set With One Or More Non-Linear Functions Using Reduced Look-Up Table With Exponentially Varying Step-Size - A digital signal processor and method are disclosed having an instruction set with one or more non-linear functions using a look-up table of reduced size and exponentially varying step-sizes. A digital signal processor evaluates a non-linear function for a value, x, by obtaining at least two values from at least one look-up table for the non-linear function that are near the value, x, wherein the at least one look-up table stores a subset of values for the non-linear function using exponentially-varying step sizes; and interpolating the at least two obtained values lo to obtain a result, y. A position of a leading zero in the value, x, can be used as an index into the at least one look-up table. The interpolation can comprise, for example, a linear interpolation or a polynomial interpolation. A modulo arithmetic operation can optionally be employed for a periodic non-linear function. | 06-03-2010 |

20100138465 | Digital Signal Processor With One Or More Non-Linear Functions Using Factorized Polynomial Interpolation - A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation. | 06-03-2010 |

20100138468 | Digital Signal Processor Having Instruction Set With One Or More Non-Linear Complex Functions - Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel. | 06-03-2010 |

20100197264 | UPLINK CHANNEL ESTIMATION - In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions. | 08-05-2010 |

20100198893 | Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look-Up Table - A digital signal processor is provided having an instruction set with an x | 08-05-2010 |

20100198894 | Digital Signal Processor Having Instruction Set With An Exponential Function Using Reduced Look-Up Table - A digital signal processor is provided having an instruction set with an exponential function that uses a reduced look-up table. The disclosed digital signal processor evaluates an exponential function for an input value, x, by decomposing the input value, x, to an integer part, N, a first fractional part, q | 08-05-2010 |

20100198895 | Digital Signal Processor Having Instruction Set With A Logarithm Function Using Reduced Look-Up Table - A digital signal processor is provided having an instruction set with a logarithm function that uses a reduced look-up table. The disclosed digital signal processor evaluates a logarithm function for an input value, x, by decomposing the input value, x, to a first part, N, a second part, q, and a remaining part, r, wherein the first part, N, is identified by a position of a most significant bit of the input value, x, and the second part, q, is comprised of a number of bits following the most significant bit, wherein the number is small relative to a number of bits in the input value, x; obtaining a value | 08-05-2010 |

20100245136 | Methods and Apparatus for Whitening Quantization Noise in a Delta-Sigma Modulator Using Dither Signal - Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator. | 09-30-2010 |

20100245137 | Methods and Apparatus for Look-Ahead Block Processing in Predictive Delta-Sigma Modulators - Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values. | 09-30-2010 |

20100245138 | METHODS AND APPARATUS FOR DECORRELATING QUANTIZATION NOISE IN A DELTA-SIGMA MODULATOR - Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. | 09-30-2010 |

20100304687 | METHODS AND APPARATUS FOR SIMULTANEOUS ESTIMATION OF FREQUENCY OFFSET AND CHANNEL RESPONSE FOR MU-MIMO OFDMA - Methods and apparatus are provided for simultaneous estimation of frequency offset and channel response for a communication system, such as a MU-MIMO communication system. An iterative method is provided for estimating frequency offset and channel response for a plurality of frequency resources. The channel response is estimated for a set of users sharing a given one of the frequency resources. In addition, the frequency offset is estimated for the users in the set, wherein the channel response and frequency offset of users not in the set are maintained at their latest updated values. Initially, the channel response of a user can be an ideal channel response and the frequency offset can be approximately zero. | 12-02-2010 |

20110051867 | METHODS AND APPARATUS FOR WIRELESS CHANNEL ESTIMATION USING INTERPOLATION ELIMINATION IN THE EIGEN DOMAIN - Methods and apparatus are provided for wireless channel estimation using interpolation elimination in the Eigen domain. Channel components at known OFDM symbol locations are interpolated to other OFDM symbol locations. Methods and apparatus are provided for interpolating in the Eigen domain between reference signals (i.e., training signals) to estimate the equalizer coefficients with a reduced complexity. In particular, one aspect of the present invention performs the required interpolation before a required matrix inversion in the Eigen domain. | 03-03-2011 |

20110243281 | PIPELINED DECISION-FEEDBACK UNIT IN A REDUCED-STATE VITERBI DETECTOR WITH LOCAL FEEDBACK - A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state. | 10-06-2011 |

20110310944 | LONG TERM EVOLUTION (LTE) UPLINK CANONICAL CHANNEL ESTIMATION - A method and system for canonical channel estimation in the Long Term Evolution uplink where a multi-frequency signal is generated and then converted to frequency spectrum which is then convolved in the frequency domain with a truncated window function to obtain a time domain channel impulse response. The time domain channel impulse response can be then transformed to a frequency domain to produce a down sampled user channel response, which can be then linearly interpolated to provide a channel estimate for a plurality of subcarriers. Such an approach achieves channel estimation within Long Term Evolution at only canonical locations to reduce complexity without loss in channel entropy. | 12-22-2011 |

20120106316 | Method and Apparatus for Cross-Talk Cancellation in Frequency Division Multiplexed Transmission Systems - A method and apparatus are disclosed for canceling cross-talk in a frequency-division multiplexed communication system. The disclosed frequency-division multiplexed communication system employs multiple carriers having overlapping channels and provides an improved cross-talk cancellation mechanism to address the resulting interference. Bandwidth compression is achieved using n level amplitude modulation in each frequency band. An FDM receiver is also disclosed that decomposes the received broadband signal into each of its respective frequency bands and returns the signal to baseband in the analog domain. Analog requirements are relaxed by removing cross-talk from adjacent RF channels, from image bands, and minimizing the performance degradation caused by In-phase and Quadrature-phase (I/Q) phase and gain mismatches in modulators and demodulators. The disclosed transmitter or receiver (or both) can be fabricated on a single integrated circuit. | 05-03-2012 |

20120128056 | METHOD AND APPARATUS FOR JOINT EQUALIZATION AND DECODING OF MULTIDIMENSIONAL CODES TRANSMITTED OVER MULTIPLE SYMBOL DURATIONS - A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. | 05-24-2012 |

20130028342 | UPLINK CHANNEL ESTIMATION - In one embodiment, a receiver is provided for use in a multiple-input system that includes a receiving antenna receiving a time-domain signal corresponding to a plurality of signals transmitted from a plurality of transmitting antennas. The receiver includes: (a) a transform unit adapted to transform the time-domain signal into a frequency-domain signal; (b) a channel estimation unit adapted to estimate, based on the frequency-domain signal and a frequency-domain pilot signal, a combined transfer function corresponding to a plurality of transfer functions of respective channels between the plurality of transmitting antennas and the receiving antenna; and (c) a channel separation unit including a plurality of frequency-domain convolution units that separate the combined transfer function into a plurality of estimated channel transfer functions. | 01-31-2013 |

20130080855 | METHODS AND APPARATUS FOR SEARCH SPHERE LINEAR BLOCK DECODING - A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors. | 03-28-2013 |