Patent application number | Description | Published |
20080213079 | Apparatus and Method for Separating and Transporting Substrates - The invention relates in particular to the separation and transportation of a disc shaped substrate ( | 09-04-2008 |
20100062184 | Method and Apparatus for the Surface Modification of Flat Substrates - The invention in general relates to the single-sided wet chemical surface modification as in particular the coating of flat substrates. In particular, the present invention relates to a method as well as to an apparatus for the coating of substrates in the course of the production of thin film solar cells or modules made from glass, metal, or plastic with metallic compounds such as i.e. cadmium sulphide or zinc sulphide. | 03-11-2010 |
20110097160 | METHOD AND APPARATUS FOR THE TRANSPORTING OF OBJECTS - The present invention relates to methods and apparatuses for the transporting of substantially flat, freely movable objects, wherein at least the holding and guiding takes place by use of a streaming liquid. | 04-28-2011 |
20120248068 | Process Module for the Inline-Treatment of Substrates - The present invention relates to an apparatus and a method for the fluidic inline-treatment of flat substrates with at least one process module. In particular, the invention relates to such a treatment during the gentle and controlled transport of the substrates, wherein the treatment can also just relate to the transport of the substrates. | 10-04-2012 |
Patent application number | Description | Published |
20140101358 | BYTE SELECTION AND STEERING LOGIC FOR COMBINED BYTE SHIFT AND BYTE PERMUTE VECTOR UNIT - Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch. | 04-10-2014 |
20140129809 | BYTE SELECTION AND STEERING LOGIC FOR COMBINED BYTE SHIFT AND BYTE PERMUTE VECTOR UNIT - Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch. | 05-08-2014 |
20150067298 | SPLITABLE AND SCALABLE NORMALIZER FOR VECTOR DATA - A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position. | 03-05-2015 |
20150067299 | SPLITABLE AND SCALABLE NORMALIZER FOR VECTOR DATA - A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position. | 03-05-2015 |
Patent application number | Description | Published |
20100174764 | REUSE OF ROUNDER FOR FIXED CONVERSION OF LOG INSTRUCTIONS - A method for converting a signed fixed point number into a floating point number that includes reading an input number corresponding to a signed fixed point number to be converted, determining whether the input number is less than zero, setting a sign bit based upon whether the input number is less than zero or greater than or equal to zero, computing a first intermediate result by exclusive-ORing the input number with the sign bit, computing leading zeros of the first intermediate result, padding the first intermediate result based upon the sign bit, computing a second intermediate result by shifting the padded first intermediate result to the left by the leading zeros, computing an exponent portion and a fraction portion, conditionally incrementing the fraction portion based on the sign bit, correcting the exponent portion and the fraction portion if the incremented fraction portion overflows, and returning the floating point number. | 07-08-2010 |
20100199074 | INSTRUCTION SET ARCHITECTURE WITH DECOMPOSING OPERANDS - Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor. | 08-05-2010 |
20120110271 | MECHANISM TO SPEED-UP MULTITHREADED EXECUTION BY REGISTER FILE WRITE PORT REALLOCATION - Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register file using a first write port of the first register file and write results of a second group of execution units associated with a second register file into the second register file using a first write port of the second register file. The system, apparatus, and process may also include the ability to connect, in a shared register file mode, results of the second group of execution units to a second write port of the first register file and connect, in a split register file mode, results of a part of the first group of execution units to the second write port of the first register file. | 05-03-2012 |
20120128149 | APPARATUS AND METHOD FOR CALCULATING AN SHA-2 HASH FUNCTION IN A GENERAL PURPOSE PROCESSOR - Various systems, apparatuses, processes, and/or products may be used to calculate an SHA-2 hash function in a general-purpose processor. In some implementations, a system, apparatus, process, and/or product may include the ability to calculate at least one SHA-2 sigma function by using an execution unit adapted for performing a processor instruction, the execution unit including an integrated circuit primarily designed for calculating the SHA-2 sigma function(s), and calculating the SHA-2 hash function with general-purpose hardware processing components of the processor based on the sigma function(s). In certain implementations, the calculation of the SHA-2 sigma function(s) can be performed by the integrated circuit within a single instruction, allowing for a faster calculation of the SHA-2 hash function. | 05-24-2012 |
20120150933 | METHOD AND DATA PROCESSING UNIT FOR CALCULATING AT LEAST ONE MULTIPLY-SUM OF TWO CARRY-LESS MULTIPLICATIONS OF TWO INPUT OPERANDS, DATA PROCESSING PROGRAM AND COMPUTER PROGRAM PRODUCT - Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus. | 06-14-2012 |
20130159666 | REDUCING ISSUE-TO-ISSUE LATENCY BY REVERSING PROCESSING ORDER IN HALF-PUMPED SIMD EXECUTION UNITS - Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction. | 06-20-2013 |
20140019780 | ACTIVE POWER DISSIPATION DETECTION BASED ON ERRONOUS CLOCK GATING EQUATIONS - A method detects active power dissipation in an integrated circuit. The method includes receiving a hardware design for the integrated circuit having one or more clock domains, wherein the hardware design comprises a local clock buffer for a clock domain, wherein the local clock buffer is configured to receive a clock signal and an actuation signal. The method includes adding instrumentation logic to the design for the clock domain, wherein the instrumentation logic is configured to compare a first value of the actuation signal determined at a beginning point of a test period to a second value of the actuation signal determined at a time when the clock domain is in an idle condition. The method includes detecting the clock domain includes unintended active power dissipation, in response to the first value of the actuation signal not being equal to the second value of the actuation signal. | 01-16-2014 |
20140075153 | REDUCING ISSUE-TO-ISSUE LATENCY BY REVERSING PROCESSING ORDER IN HALF-PUMPED SIMD EXECUTION UNITS - Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction. | 03-13-2014 |
Patent application number | Description | Published |
20140044529 | SEALING OF THE FLOW CHANNEL OF A TURBOMACHINE - A turbomachine having a flow channel and a housing radially surrounding the flow channel, a plurality of stationary and moving blades being situated in the flow channel, stationary blades being situated adjacent to the moving blades in the axial direction, and the stationary blades having at least one stationary blade hook which engages with at least one housing hook for the purpose of connecting the stationary blades to the housing. A sealing and lining element is situated in the radial direction between the moving blades adjacent to the stationary blades and the housing, and has a sealing structure interacting with blade tips of the moving blades. A heat protection element is provided in the area between the sealing and lining element and the housing, and a sealing element being situated on the heat protection element for the purpose of sealing contact with the housing hook. | 02-13-2014 |
20140044538 | CLAMPING RING FOR A TURBOMACHINE - A turbomachine having a flow channel ( | 02-13-2014 |
20140105731 | AXIAL SEAL IN A CASING STRUCTURE FOR A FLUID FLOW MACHINE - A casing structure for a fluid flow machine, in particular for a gas turbine or an aircraft engine, including an outer casing wall and an inner casing wall, which annularly surround a flow channel of the fluid flow machine and are spaced apart in a radial direction with respect to the flow channel. At least one cavity is formed between the inner and outer casing walls. The cavity is axially divided into at least two regions which are separated from each other by an axial seal in such a way that different pressure conditions are created according to the axial position of these regions, which different pressure conditions correspond to the pressure conditions in the flow channel. A corresponding fluid flow machine such as, for example, an aircraft engine. | 04-17-2014 |
20140112767 | COOLING-AIR GUIDANCE IN A HOUSING STRUCTURE OF A TURBOMACHINE - A housing structure for a turbomachine, the housing structure annularly surrounding, at least partially, a flow channel ( | 04-24-2014 |
20150037161 | METHOD FOR MOUNTING A GAS TURBINE BLADE IN AN ASSOCIATED RECEIVING RECESS OF A ROTOR BASE BODY - A gas turbine blade in an associated receiving recess of a rotor base body includes a slot in the blade root and has the shape of a straight cylinder. A blade retaining plate has a first securing region and a second securing region interconnected by a shaft region; the shaft region having the shape of a straight cylinder configured to conform to the slot of the blade root. The shaft region comes to rest on a bottom of the receiving recess of the rotor base body; the first securing region being reshaped to form a first limit stop for a first end wall of the blade root; and the second securing region being reshaped to allow the blade root to be inserted along the insertion direction into the receiving recess. The second securing region of the blade retaining plate is subsequently reshaped to allow the second securing region to form a second limit stop for a second end wall of the blade root facing opposite the first end wall, and the blade root to be secured in position in the receiving recess. | 02-05-2015 |