Patent application number | Description | Published |
20080210976 | Semiconductor Device Having an Implanted Precipitate Region and a Method of Manufacture Therefor - The present invention provides a semiconductor device, a method of manufacture therefor and an integrated circuit including the same. The semiconductor device | 09-04-2008 |
20100022062 | TRANSITOR HAVING A GERMANIUM IMPLANT REGION LOCATED THEREIN AND A METHOD OF MANUFACTURE THEREFOR - The present invention provides a transistor | 01-28-2010 |
20120241829 | Low Leakage Capacitor for Analog Floating-Gate Integrated Circuits - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 09-27-2012 |
20130130450 | LOW LEAKAGE CAPACITOR FOR ANALOG FLOATING-GATE INTEGRATED CIRCUITS - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 05-23-2013 |
20130334659 | Multiple Depth Vias In An Integrated Circuit - An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias. | 12-19-2013 |
20140001526 | Analog Floating-Gate Capacitor with Improved Data Retention in a Silicided Integrated Circuit | 01-02-2014 |
20140295631 | ANALOG FLOATING-GATE CAPACITOR WITH IMPROVED DATA RETENTION IN A SILICIDED INTEGRATED CIRCUIT - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate. | 10-02-2014 |
20150187598 | HIGH PRECISION CAPACITOR DIELECTRIC - A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre-and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric. | 07-02-2015 |
20150187938 | LOW COST DEMOS TRANSISTOR WITH IMPROVED CHC IMMUNITY - An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate. | 07-02-2015 |