Patent application number | Description | Published |
20090159927 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION - An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance C | 06-25-2009 |
20090184373 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device is provided which has a semiconductor substrate. An active cell area having at least one active cell is formed in the semiconductor substrate, wherein at least sections of the active cell area are surrounded by an edge termination region. An integrated gate runner structure is arranged at least partially in the edge termination region and has at least one low electrical resistance portion and at least one high electrical resistance portion which are electrically connected in series with each other. | 07-23-2009 |
20090321818 | SEMICONDUCTOR COMPONENT WITH TWO-STAGE BODY ZONE - A semiconductor component with a two-stage body zone. One embodiment provides semiconductor component including a drift zone, and a compensation zone of a second conduction type. The compensation zone is arranged in the drift zone. A source zone and a body zone is provided. The body zone is arranged between the source zone and the drift zone. A gate electrode is arranged adjacent to the body zone. The body zone has a first body zone section and a second body zone section, which are adjacent to one another along the gate dielectric and of which the first body zone section is doped more highly than the second body zone section. | 12-31-2009 |
20100025748 | SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 02-04-2010 |
20110241104 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION - An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance C | 10-06-2011 |
20110244646 | SEMICONDUCTOR WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 10-06-2011 |
20130009227 | SEMICONDUCTOR DEVICE WITH A DYNAMIC GATE-DRAIN CAPACITANCE - A semiconductor device with a dynamic gate drain capacitance. One embodiment provides a semiconductor device. The device includes a semiconductor substrate, a field effect transistor structure including a source region, a first body region, a drain region, a gate electrode structure and a gate insulating layer. The gate insulating layer is arranged between the gate electrode structure and the body region. The gate electrode structure and the drain region partially form a capacitor structure including a gate-drain capacitance configured to dynamically change with varying reverse voltages applied between the source and drain regions. The gate-drain capacitance includes at least one local maximum at a given threshold or a plateau-like course at given reverse voltage. | 01-10-2013 |
20140124851 | Radiation-Hardened Power Semiconductor Devices and Methods of Forming Them - According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C. | 05-08-2014 |
20140231909 | Super Junction Semiconductor Device Comprising Implanted Zones - In a semiconductor substrate with a first surface and a working surface parallel to the first surface, columnar first and second super junction regions of a first and a second conductivity type are formed. The first and second super junction regions extend in a direction perpendicular to the first surface and form a super junction structure. The semiconductor portion is thinned such that, after the thinning, a distance between the first super junction regions having the second conductivity type and a second surface obtained from the working surface does not exceed 30 μm. Impurities are implanted into the second surface to form one or more implanted zones. The embodiments combine super junction approaches with backside implants enabled by thin wafer technology. | 08-21-2014 |
20140231910 | Manufacturing a Super Junction Semiconductor Device and Semiconductor Device - A super junction semiconductor device includes a semiconductor portion with a first surface and a parallel second surface. A doped layer of a first conductivity type is formed at least in a cell area. Columnar first super junction regions of a second, opposite conductivity type extend in a direction perpendicular to the first surface. Columnar second super junction regions of the first conductivity type separate the first super junction regions from each other. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 μm. The on-state or forward resistance of low-voltage devices rated for reverse breakdown voltages below 1000 V can be defined by the resistance of the super junction structure. | 08-21-2014 |
20140327069 | Semiconductor Device with a Super Junction Structure Based On a Compensation Structure with Compensation Layers and Having a Compensation Rate Gradient - A super junction structure is formed in a semiconductor portion of a super junction semiconductor device. The super junction structure includes a compensation structure with a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The compensation structure lines at least sidewall portions of compensation trenches that extend between semiconductor mesas along a vertical direction perpendicular to a first surface of the semiconductor portion. Within the super junction structure and a pedestal layer that may adjoin the super junction structure, a sign of a lateral compensation rate changes along the vertical direction resulting in a local peak of a vertical electric field gradient and to improved avalanche ruggedness. | 11-06-2014 |
20150115354 | Semiconductor Device - The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer. | 04-30-2015 |
20150115358 | Semiconductor Device - The present disclosure provides a semiconductor device, including a compensation area that includes p-regions and n-regions, a plurality of transistor cells including gate electrodes on the compensation area, and one or more interconnections for electrically connecting gate electrodes. The gate electrodes may have a width smaller than ½ of a pitch of the cells. | 04-30-2015 |
20150145038 | SUPER JUNCTION SEMICONDUCTOR DEVICE HAVING COLUMNAR SUPER JUNCTION REGIONS - A super junction semiconductor device includes a semiconductor portion with a first surface and a second surface parallel to the first surface. The semiconductor portion includes a doped layer of a first conductivity type formed at least in a cell area. The super junction semiconductor device further includes columnar first super junction regions of a second, opposite conductivity type extending in a direction perpendicular to the first surface and separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A distance between the first super junction regions and the second surface does not exceed 30 μm. | 05-28-2015 |