Patent application number | Description | Published |
20080203438 | DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS - A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2 | 08-28-2008 |
20080225567 | METHOD AND STRUCTURE FOR INCREASING EFFECTIVE TRANSISTOR WIDTH IN MEMORY ARRAYS WITH DUAL BITLINES - A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more. | 09-18-2008 |
20080225578 | STRUCTURE FOR INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES - A memory structure, includes: an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; a rectifying element in series with each of the resistive memory devices at a second end thereof; an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more. | 09-18-2008 |
20080232160 | RECTIFYING ELEMENT FOR A CROSSPOINT BASED MEMORY ARRAY ARCHITECTURE - An asymmetrically programmed memory material (such as a solid electrolyte material) is described for use as a rectifying element for driving symmetric or substantially symmetric resistive memory elements in a crosspoint memory architecture. A solid electrolyte element (SE) has very high resistance in the OFF state and very low resistance in the ON state (because it is a metallic filament in the ON state). These attributes make it a near ideal diode. During the passage of current (during program/read/erase) of the memory element, the solid electrolyte material also programs into the low resistance state. The final state of the solid electrolyte material is reverted to a high resistance state while making sure that the final state of the memory material is the one desired. | 09-25-2008 |
20080280401 | INCREASING EFFECTIVE TRANSISTOR WITDTH IN MEMORY ARRAYS WITH DUAL BITLINES - A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more. | 11-13-2008 |
20080304307 | USE OF A SYMMETRIC RESISTIVE MEMORY MATERIAL AS A DIODE TO DRIVE SYMMETRIC OR ASYMMETRIC RESISTIVE MEMORY - A symmetrically resistive memory material (such as a phase change material) is described for use as a rectifying element for driving symmetric or asymmetric resistive memory elements in a crosspoint memory architecture. The crosspoint architecture has a plurality of electrodes and a plurality of crossbar elements, with each crossbar element being disposed between a first and a second electrode. The crossbar element is made of a symmetric resistive memory element used as a rectifier in series with a symmetric or asymmetric resistive memory element. | 12-11-2008 |
20080314738 | Electrolytic Device Based on a Solution-Processed Electrolyte - The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device. | 12-25-2008 |
20080314739 | ELECTROLYTIC DEVICE BASED ON A SOLUTION-PROCESSED ELECTROLYTE - The present disclosure relates to a solid electrolyte device comprising an amorphous chalcogenide solid active electrolytic layer; first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is located between the first and second metallic layers. The amorphous chalcogenide solid active electrolytic layer is prepared by obtaining a solution of a hydrazine-based precursor to a metal chalcogenide; applying the solution onto a substrate; and thereafter annealing the precursor to convert the precursor to the amorphous metal chalcogenide. The present disclosure also relates to processes for fabricating the solid electrolyte device. | 12-25-2008 |
20100248441 | MULTI-BIT HIGH-DENSITY MEMORY DEVICE AND ARCHITECTURE AND METHOD OF FABRICATING MULTI-BIT HIGH-DENSITY MEMORY DEVICES - A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins. | 09-30-2010 |
20110141801 | USE OF SYMMETRIC RESISTIVE MEMORY MATERIAL AS A DIODE TO DRIVE SYMMETRIC OR ASYMMETRIC RESISTIVE MEMORY - A crosspoint array is made up of a plurality of bitlines and wordlines and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline, and each crossbar element comprising at least a phase change material used as a rectifier in series with a solid electrolyte used as an asymmetric resistive memory element. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the phase change material in the crossbar elements from an OFF state to an ON state; a second set of voltages to read or program the solid electrolyte, and a third set of voltages to transition the phase change material from an ON state to an OFF state. | 06-16-2011 |
20110227023 | BACKEND OF LINE (BEOL) COMPATIBLE HIGH CURRENT DENSITY ACCESS DEVICE FOR HIGH DENSITY ARRAYS OF ELECTRONIC COMPONENTS - A device is disclosed having a M | 09-22-2011 |
20120243291 | Crosspoint Array and Method of Use with a Crosspoint Array Having Crossbar Elements Having a Solid Electrolyte Material Used as a Rectifier with a Symmetric or Substantially Symmetric Resistive Memory - A crosspoint array has been shown having a plurality of bitlines and wordlines; and a plurality of crossbar elements, with each crossbar element being disposed between a bitline and a wordline and with each crossbar element having at least a solid electrolyte material used as a rectifier in series with a symmetric or substantially symmetric resistive memory node. The crossbar elements are responsive to the following voltages: a first set of voltages to transition the solid electrolyte in the crossbar elements from an OFF state to an ON state, a second set of voltages to read or program the symmetric resistive memory, and a third set of voltages to transition solid electrolyte from an ON state to an OFF state. | 09-27-2012 |
20130039110 | 3D ARCHITECTURE FOR BIPOLAR MEMORY USING BIPOLAR ACCESS DEVICE - Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer. | 02-14-2013 |
20130044532 | LOW TEMPERATURE BEOL COMPATIBLE DIODE HAVING HIGH VOLTAGE MARGINS FOR USE IN LARGE ARRAYS OF ELECTRONIC COMPONENTS - A crystalline semiconductor Schottky barrier-like diode sandwiched between two conducting electrodes is in series with a memory element, a word line and a bit line, wherein the setup provides voltage margins greater than 1V and current densities greater than 5×10 | 02-21-2013 |
20130223125 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING BIPOLAR PROGRAMMING - A system and method for operating a bipolar memory cell array including a bidirectional access diode. The system includes a column voltage. The column voltage switch includes column voltages and an output electrically coupled to the bidirectional access diode. The column voltages include at least one write-one column voltage and at least one write-zero column voltage. The system also includes a row voltage switch. The row voltage switch includes row voltages and an output electrically coupled to the bidirectional access diode. The row voltages include at least one write-one row voltage and at least one write-zero row voltage. The system further includes a column decoder and a row decoder electrically coupled to a select line of the column voltage switch and row voltage switch, respectively. The system includes a write driver electrically coupled to the select lines of the row and column switches. | 08-29-2013 |
20130322153 | NON-VOLATILE MEMORY CROSSPOINT REPAIR - A device for use with a memory cross-point array of elements, each of which comprises a selection device in series with a state-holding device, in one embodiment includes a controller, configured to apply at least one voltage and/or current pulse to a selected one or more of the elements, said selected one or more of the elements including a partially- or completely-shorted selection device, so that said partially- or completely-shorted selection device passes enough current so as to damage its corresponding state-holding device and place said corresponding state-holding device in a highly resistive state, while any other selection device that is not partially- or completely-shorted passes less current so that the state-holding device corresponding to said other selection device remains unaffected. Additional systems and methods are also presented. | 12-05-2013 |
20140022850 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING - A system and method for operating a unipolar memory cell array including a bidirectional access diode. The system includes a column voltage switch electrically coupled to a plurality of column voltages. The column voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of column voltages includes at least one select column voltage and one deselect column voltage. The system includes a row voltage switch electrically coupled to a plurality of row voltages. The row voltage switch includes an output electrically coupled to the bidirectional access diode. The plurality of row voltages includes at least one select row voltage and one deselect row voltage. The system includes a column and row decoder electrically coupled to a select line of the column and row voltage switches, respectively. | 01-23-2014 |
20140022851 | DECODING SCHEME FOR BIPOLAR-BASED DIODE THREE-DIMENSIONAL MEMORY REQUIRING UNIPOLAR PROGRAMMING - A system and method for operating a unipolar memory cell array including a bidirectional access diode. An example embodiment is a method including determining if the operating state of the unipolar memory cell is in a select state or a deselect state and the programming state is a read state or a write state. The method switches a column voltage switch based on the operating state and the programming state of the unipolar memory cell. The method further switches a row voltage switch based on the operating state and the programming state of the unipolar memory cell. | 01-23-2014 |