Patent application number | Description | Published |
20090055631 | Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search - A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time. | 02-26-2009 |
20140006750 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS | 01-02-2014 |
20140006852 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS | 01-02-2014 |
20140133208 | MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS - Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions. | 05-15-2014 |
20140133209 | MEMORY ARCHITECTURES HAVING WIRING STRUCTURES THAT ENABLE DIFFERENT ACCESS PATTERNS IN MULTIPLE DIMENSIONS - Multi-dimensional memory architectures are provided having access wiring structures that enable different access patterns in multiple dimensions. Furthermore, three-dimensional multiprocessor systems are provided having multi-dimensional cache memory architectures with access wiring structures that enable different access patterns in multiple dimensions. | 05-15-2014 |
20140281378 | THREE-DIMENSIONAL COMPUTER PROCESSOR SYSTEMS HAVING MULTIPLE LOCAL POWER AND COOLING LAYERS AND A GLOBAL INTERCONNECTION STRUCTURE - A computer processor system includes a plurality of multi-chip systems that are physically aggregated and conjoined. Each multi-chip system includes a plurality of chips that are conjoined together, and a local interconnection and input/output wiring layer. A global interconnection network is connected to the local interconnection and input/output wiring layer of each multi-chip system to interconnect the multi-chip systems together. One or more of the multi-chip systems includes a plurality of processor chips that are conjoined together. | 09-18-2014 |
20150032962 | THREE-DIMENSIONAL PROCESSING SYSTEM HAVING MULTIPLE CACHES THAT CAN BE PARTITIONED, CONJOINED, AND MANAGED ACCORDING TO MORE THAN ONE SET OF RULES AND/OR CONFIGURATIONS - Three-dimensional processing systems are provided which have multiple layers of conjoined chips, wherein one or more chip layers include processor cores that share cache hierarchies over multiple chip layers. The caches can be partitioned, conjoined, and managed according to various sets of rules and configurations. | 01-29-2015 |
20150074624 | Enhanced Case-Splitting Based Property Checking - An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model. | 03-12-2015 |
20150074628 | Enhanced Case-Splitting Based Property Checking - An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model. | 03-12-2015 |
Patent application number | Description | Published |
20080270705 | METHOD AND APPARATUS FOR APPLICATION-SPECIFIC DYNAMIC CACHE PLACEMENT - One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the virtual partitions to which the load/store instruction is assigned. | 10-30-2008 |
20090259705 | METHOD AND STRUCTURE FOR PROVABLY FAIR RANDOM NUMBER GENERATOR - A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator. | 10-15-2009 |
20090282178 | Bounded Starvation Checking of an Arbiter Using Formal Verification - A system for formal verification of bounded fairness properties of pseudo random number generators and arbiters that use random priority-based arbitration schemes. The formal verification system determines an upper bound of a request-to-grant delay of an arbiter in terms of a number of complete random sequences. The formal verification system also determines, in terms of a number of clock cycles, an upper bound and a lower bound of a length of a complete random sequence in the random number sequence generated by a random number generator used by the arbiter. The formal verification system then determines a worst case request-to-grant delay bounds of the arbiter system, in terms of a number of clock cycles, by combining the upper bound of the request-to-grant delay of the arbiter with the upper bound of the length of the complete random sequence and the lower bound of the length of the complete random sequence. | 11-12-2009 |
20120323982 | METHOD AND STRUCTURE FOR PROVABLY FAIR RANDOM NUMBER GENERATOR - A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator. | 12-20-2012 |
20130283006 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME - Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image. | 10-24-2013 |
20130283008 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME - Three-dimensional (3-D) processor structures are provided which are constructed by connecting processors in a stacked configuration. For example, a processor system includes a first processor chip comprising a first processor, and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively configure the first and second processors of the first and second processor chips to operate in one of a plurality of operating modes, wherein the processors can be selectively configured to operate independently, to aggregate resources, to share resources, and/or be combined to form a single processor image. | 10-24-2013 |
20130283009 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME - Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution. | 10-24-2013 |
20130283010 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME - Three-dimensional (3-D) processor devices are provided, which are constructed by connecting processors in a stacked configuration. For instance, a processor system includes a first processor chip comprising a first processor and a second processor chip comprising a second processor. The first and second processor chips are connected in a stacked configuration with the first and second processors connected through vertical connections between the first and second processor chips. The processor system further includes a mode control circuit to selectively operate the processor system in one of a plurality of operating modes. For example, in a one mode of operation, the first and second processors are configured to implement a run-ahead function, wherein the first processor operates a primary thread of execution and the second processor operates a run-ahead thread of execution. | 10-24-2013 |
Patent application number | Description | Published |
20090175238 | Multi-Channel Assignment Method For Multi-Radio Multi-Hop Wireless Mesh Networks - Techniques are described for automatically determining quasi-static per-link channel assignments for each radio in multiple-hop mesh networks having nodes with two or more radios and where only a small number of channels is available for use in the network. The method optimally assigns the channels to the radios of all of the nodes in the network so as to achieve the lowest interference among links and the highest possible bandwidth. | 07-09-2009 |
20090190531 | Mesh Node Mobility Across Static and Mobile Mesh Networks - Methods and systems for mobility of mobile nodes in mesh networks are taught wherein the mobile mesh nodes choose an attachment point to another mesh node based on predetermined criteria, such as the characteristics of the attachment point's path to a reference destination, and other factors local to the attachment point, such as load and available capacity. The mobile nodes forward packets on each other's behalf. Static and mobile nodes and the links between them are treated differently from each other in view of their respectively different properties. A special metric is used for paths that include mobile links in addition to the static mesh links and wired mesh links. Mobility is handled completely transparently to any client devices attached to the mesh nodes, where this attachment could be wireless or wired. | 07-30-2009 |
20130033987 | METHOD FOR ENABLING THE EFFICIENT OPERATION OF ARBITRARILY INTERCONNECTED MESH NETWORKS - Wireless mesh networks (or “meshes”) are enabled for arbitrary interconnection to each other and may provide varying levels of coverage and redundancy as desired. Interoperability between meshes having differing configurations, internal operations, or both, may be freely intermixed and inter-operated in unrestricted combination. Enhanced explicit inter-bridge control protocols operate using pre-existing control packets. Pre-existing broadcast packet floods are used to learn the best paths across interconnected meshes (termed a “multi-mesh”). Enhanced routing protocols operating within each mesh may optionally examine information limited to the respective mesh when forwarding traffic, thus enabling robust multi-mesh scaling with respect to memory and processing time required by the routing protocols. Communication scalability is improved by enabling frequency diversity across the multi-mesh by configuring meshes within interference range of each other for operation at a plurality of frequencies. Each mesh may operate at a respective non-interfering frequency. | 02-07-2013 |
20130329582 | Mesh Node Mobility Across Static and Mobile Mesh Networks - Methods and systems for mobility of mobile nodes in mesh networks are taught wherein the mobile mesh nodes choose an attachment point to another mesh node based on predetermined criteria, such as the characteristics of the attachment point's path to a reference destination, and other factors local to the attachment point, such as load and available capacity. The mobile nodes forward packets on each other's behalf. Static and mobile nodes and the links between them are treated differently from each other in view of their respectively different properties. A special metric is used for paths that include mobile links in addition to the static mesh links and wired mesh links. Mobility is handled completely transparently to any client devices attached to the mesh nodes, where this attachment could be wireless or wired. | 12-12-2013 |