Patent application number | Description | Published |
20080235461 | Technique and apparatus for combining partial write transactions - A bridge includes a memory to establish a transaction table and write combining windows. Each write combining window is associated with a cache line and is subdivided into subwindows; and each of the subwindows is associated with a partial cache line. The bridge includes a controller to determine whether an incoming partial write transaction conflicts with a transaction stored in the transaction table. If a conflict occurs, the controller uses the write combining windows to combine the partial write transaction with another partial write transaction if one of the partial write combining windows is available. The controller issues a retry signal to a processor originating the partial write transaction if none of the partial write combining windows are available. | 09-25-2008 |
20080320249 | FULLY BUFFERED DIMM READ DATA SUBSTITUTION FOR WRITE ACKNOWLEDGEMENT - A memory controller uses a scheme to retire two entries from a replay queue due to a single non-error response. Advantageously, entries in a replay queue may be retired earlier than conventional systems, minimizing the size of the replay queue. | 12-25-2008 |
20090171875 | SYSTEMS, METHODS AND APPARATUSES FOR RANK COORDINATION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for rank coordination. In some embodiments, a host includes rank coordination logic. The rank coordination logic may include performance measurement logic to measure a performance of a memory channel and dwell period control logic to select a length of a dwell period based, at least in part, on the performance of the memory channel. Other embodiments are described and claimed. | 07-02-2009 |
20090172295 | In-memory, in-page directory cache coherency scheme - In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor. | 07-02-2009 |
20090172681 | SYSTEMS, METHODS AND APPARATUSES FOR CLOCK ENABLE (CKE) COORDINATION - Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed. | 07-02-2009 |
20090300289 | Reducing back invalidation transactions from a snoop filter - In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed. | 12-03-2009 |
20090319717 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEMS AND ASSOCIATED METHODS - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact. | 12-24-2009 |
20100005248 | PSEUDO LEAST RECENTLY USED REPLACEMENT/ALLOCATION SCHEME IN REQUEST AGENT AFFINITIVE SET-ASSOCIATIVE SNOOP FILTER - The storage locations of a snoop filter are segregated into a number of groups, and some groups are associated with some processors in a system. When new data enter a cache line of a processor, one of the storage locations associated with the processor is selected for further operations. | 01-07-2010 |
20100169585 | Dynamic updating of thresholds in accordance with operating conditons - In some embodiments, a memory control device includes a sensor positioned remotely from a memory device, a register to store an offset value, the offset value corresponding to a difference between a temperature reading of the sensor and an estimated actual temperature of the memory device, and a controller to control an operation of the memory device, wherein the controller is configured to read the offset value from the register and control the operation of the memory device in accordance with the offset value. The controller may be configured to dynamically update the offset value during an operation of the memory device. Other embodiments are disclosed and claimed. | 07-01-2010 |
20110185101 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact. | 07-28-2011 |
20120185706 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DYNAMIC CONTROL OF ENERGY CONSUMPTION IN POWER DOMAINS - An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit. | 07-19-2012 |
20120317328 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact. | 12-13-2012 |
20130007560 | RANK-SPECIFIC CYCLIC REDUNDANCY CHECK - Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems. | 01-03-2013 |
20130275810 | METHOD AND APPARATUS FOR INJECTING ERRORS INTO MEMORY - Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory. | 10-17-2013 |
20130332795 | RANK-SPECIFIC CYCLE REDUNDANCY CHECK - Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems. | 12-12-2013 |
20140006899 | MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SERVICEABILITY | 01-02-2014 |
20140129767 | APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY - A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.” | 05-08-2014 |
20150058524 | BIMODAL FUNCTIONALITY BETWEEN COHERENT LINK AND MEMORY EXPANSION - Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed. | 02-26-2015 |