Kageshima
Atsushi Kageshima, Yokohama-Shi JP
Patent application number | Description | Published |
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20100088451 | ARCHITECTURE VERIFYING APPARATUS, ARCHITECTURE VERIFYING METHOD, AND MEDIUM STORING ARCHITECTURE VERIFYING PROGRAM - An architecture verifying apparatus includes an inputting unit receiving limitation information, a bus monitor monitoring a bus transaction to obtain bus transaction information, a module monitor monitoring a reception transaction, processing, and a transmission transaction to obtain reception transaction information, processing information, and transmission transaction information, an architecture information generator associating the limitation information and the bus transaction information with the reception transaction information, the processing information, and the transmission transaction information to generate architecture information, and an outputting unit supplying the architecture information. | 04-08-2010 |
Atsushi Kageshima, Kanagawa JP
Patent application number | Description | Published |
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20120245915 | SEMICONDUCTOR INTEGRATED CIRCUIT SIMULATION APPARATUS AND SIMULATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - According to an embodiment, a simulation apparatus has a bus architecture information acquiring module configured to acquire bus architecture information of a bus included in a semiconductor integrated circuit, a transfer size calculating module configured to calculate a transfer size conforming to a bus architecture, based on the bus architecture information which is acquired, and a simulation executing module. The simulation executing module sets a transaction converting module configured to convert a transaction from a bus initiator included in the semiconductor integrated circuit into a transaction in a size conforming to the transfer size and output the transaction to the bus, and performs simulation of the semiconductor integrated circuit. | 09-27-2012 |
Yoshiaki Kageshima, Chichibu-Shi JP
Patent application number | Description | Published |
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20140145214 | SIC EPITAXIAL WAFER AND METHOD FOR PRODUCING SAME, AND DEVICE FOR PRODUCING SIC EPITAXIAL WAFER - A SiC epitaxial wafer manufacturing method of the present invention includes: manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a surface of a SiC single crystal wafer while supplying a raw material gas into a chamber using a SIC epitaxial wafer manufacturing apparatus; and manufacturing a subsequent SiC epitaxial wafer after measuring a surface density of triangular defects originating from a material piece of an internal member of the chamber on the SiC epitaxial layer of the previously manufactured SiC epitaxial wafer. | 05-29-2014 |
20140175461 | SIC EPITAXIAL WAFER AND METHOD FOR MANUFACTURING SAME - Provided are a SiC epitaxial wafer in which the surface density of stacking faults is reduced, and a manufacturing method thereof. The method for manufacturing such a SiC epitaxial wafer comprises a step of determining a ratio of basal plane dislocations (BPD), which causes stacking faults in a SiC epitaxial film of a prescribed thickness which is formed on a SiC single crystal substrate having an off angle, to basal plane dislocations which are present on a growth surface of the SiC single crystal substrate, a step of determining an upper limit of surface density of basal plane dislocations on the growth surface of a SiC single crystal substrate used based on the above ratio, and a step of preparing a SiC single crystal substrate which has surface density equal to or less than the above upper limit, and forming a SiC epitaxial film on the SiC single crystal substrate under the same conditions as the growth conditions of the epitaxial film used in the step of determining the ratio. | 06-26-2014 |
20140190400 | EPITAXIAL WAFER MANUFACTURING DEVICE AND MANUFACTURING METHOD - Provided is an epitaxial wafer manufacturing device ( | 07-10-2014 |
20140230722 | EPITAXIAL WAFER MANUFACTURING DEVICE AND MANUFACTURING METHOD - An epitaxial wafer manufacturing device, including a shield ( | 08-21-2014 |