| Patent application number | Description | Published |
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| 20110021598 | CONTROLLED RELEASE FORMULATIONS - The invention relates to a controlled release formulation for an oral cytokine inhibitor of interleukin-1 beta converting enzyme. | 01-27-2011 |
| 20110256220 | PHARMACEUTICAL COMPOSITIONS OF 3-(6-(1-(2,2-DIFLUOROBENZO[D][1,3]DIOXOL-5-YL) CYCLOPROPANECARBOXAMIDO)-3-METHYLPYRIDIN-2-YL)BENZOIC ACID AND ADMINISTRATION THEREOF - A pharmaceutical composition comprising Compound 1, (3-(6-(1-(2,2-difluorobenzo[d][1,3]dioxol-5-yl)cyclopropanecarboxamido)-3-methylpyridin-2-yl)benzoic acid), and at least one excipient selected from: a filler, a diluent, a disintegrant, a surfactant, a binder, a glidant and a lubricant, the composition being suitable for oral administration to a patient in need thereof to treat a CFTR mediated disease such as Cystic Fibrosis. Methods for treating a patient in need thereof include administering an oral pharmaceutical formulation of Compound 1 to the patient. | 10-20-2011 |
| 20120015999 | FORMULATIONS OF (R)-1-(2,2-DIFLUOROBENZO[D] [1,3] DIOXOL-5-YL)-N-(1-(2,3-DIHYDROXYPROPYL)-6-FLUORO-2-(1-HYDROXY-2-METHYLPRO- PAN-2-YL)-1H-INDOL-5-YL)CYCLOPROPANECARBOXAMIDE - The present invention relates to formulations of (R)-1-(2,2-difluorobenzo[d][1,3]dioxol-5-yl)-N-(1-(2,3-dihydroxypropyl)-6-fluoro-2-(1-hydroxy-2-methylpropan-2-yl)-1H-indol-5-yl)cyclopropanecarboxamide (Compound 1), pharmaceutical packs or kits thereof, and methods of treatment therewith. | 01-19-2012 |
| 20120046330 | PHARMACEUTICAL COMPOSITIONS OF (R)-1-(2,2-DIFLUOROBENZO[D] [1,3]DIOXOL-5-YL)-N-(1-(2,3-DIHYDROXYPROPYL)-6-FLUORO-2-(1-HYDROXY-2-METH- YLPROPAN-2-YL)-1H-INDOL-5-YL) CYCLOPROPANECARBOXAMIDE AND ADMINISTRATION THEREOF - A pharmaceutical composition comprising Compound 1, (R)-1-(2,2-difluorobenzo[d][1,3]dioxol-5-yl)-N-(1-(2,3-dihydroxypropyl)-6-fluoro-2-(1-hydroxy-2-methylpropan-2-yl)-1H-indol-5-yl)cyclopropanecarboxamide, and at least one excipient selected from: a filler, a diluent, a disintegrant, a surfactant, a glidant and a lubricant, the composition being suitable for oral administration to a patient in need thereof to treat a CFTR mediated disease such as Cystic Fibrosis. Methods for treating a patient in need thereof include administering the pharmaceutical composition of Compound 1 are also disclosed. | 02-23-2012 |
| Patent application number | Description | Published |
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| 20090279127 | Mechanism for data extraction of variable positioned data - A method is disclosed. The method includes generating one or more Tag Logical Elements (TLEs) in a variable location within a page of an Advanced Function Presentation (AFP) document. | 11-12-2009 |
| 20120044520 | METHODS AND STRUCTURE FOR IMPROVED PRESENTATION OF JOB STATUS IN A PRINT SERVER - Methods and associated structure for displaying the status of a plurality of print jobs using a graphical user interface to present a broad overview of the status of the print jobs. Status information regarding the plurality of print jobs is received from one or more print servers. The status of each job is analyzed to associate a top-level category with each job and a status sub-category with each job. A graphical object is presented to the user to represent each of the top-level categories and each of the sub-categories within each top-level category. A count of the number of jobs associated with each graphical object may be presented to the user as a number associated with the graphical object. The graphical objects may be color-coded to indicate the level of operator intervention (if any) required for the print jobs associated with the corresponding top-level category or sub-category. | 02-23-2012 |
| 20120188580 | INSERTION OF PRINTER OPERATOR INSTRUCTIONS ONTO SEPARATOR PAGES IN A PRINT SHOP ENVIRONMENT - Systems and methods are provided for notifying operators of tasks to perform on printers by inserting operator instructions onto separator pages that are placed between print jobs. One embodiment is a print server that includes a control system and a page generator. The control system is operable to identify a print job, and to identify an operator instruction for the print job indicating a physical task for an operator to perform on a printer before the print job is printed. Also, the control system holds the print job responsive to identifying the operator instruction. The page generator generates a separator page comprising the operator instruction that indicates the physical task to perform on the printer, and transmits the separator page for printing to inform the operator of the task before the print job is printed. | 07-26-2012 |
| 20120188587 | PRINT QUEUE MANAGEMENT IN A PRINT SHOP ENVIRONMENT - Systems and methods for print queue management are provided. The system performs a queue management process to identify a print job loaded in a first queue for a first printer, and to estimate a first time to print the print job on the first printer from the first queue. The system selects a second queue for a second printer, estimates a second time to print the print job on the second printer from the second queue if the print job were moved to the second queue, and calculates a difference in printing time between the first time to print and the second time to print. The system also moves the print job from the first queue to the second queue based on the calculated difference in printing time. | 07-26-2012 |
| 20120212757 | MULTIPLE PRINT PROTOCOL CAPABILITY OF A VIRTUAL PRINTER IN A PRINT SHOP ARCHITECTURE - The systems and methods presented herein provide for seamless printer accessibility to clients regardless of the print protocols being used in their respective print jobs. A printing system includes a physical printer and a print process device operable to process a print job from a client system. The print processing device includes a virtual printer operable to detect a print protocol associated with the print job, determine that the print protocol associated with the print job conflicts with the print capabilities of the physical printer, configure the print job with the print protocol of the physical printer based on the print protocol associated with the print job, and process the print job according to the print protocol of the physical printer. In doing so, a protocol converter may map printer commands of the print protocol of the print job to printer commands of the print protocol of the printer. | 08-23-2012 |
| 20120212769 | PSEUDO JOBS IN PRINT QUEUES FOR PRINT JOB SCHEDULING - Methods and systems are provided for scheduling multiple types of print jobs in a print queue using a pseudo job. A pseudo job is a special type of non-printing job object that is added to a print queue. In one embodiment, a system includes a print queue that stores print jobs scheduled for a printer. The print queue also stores a pseudo job that defines a boundary in the queue between print jobs having a first set of print settings and print jobs having a second set of print settings. In another embodiment, a system includes a print queue, a control system, and a graphical user interface. The graphical user interface displays options for generating a pseudo job, and receives input indicating a scheduled change to a configuration of a printer. The control system generates the pseudo job based on the input, and inserts the pseudo job in the print queue. | 08-23-2012 |
| 20120212770 | PRINT JOB SCHEDULING IN A PRINT SHOP ENVIRONMENT - Methods and systems are provided for scheduling multiple types of print jobs for a printer more efficiently by scheduling jobs together that share print settings. In one embodiment, a system includes a print queue that stores print jobs scheduled for a printer. The system also includes a scheduler that receives requests to schedule a print job for the printer. The scheduler compares the print settings of the requested print job to print settings of the print jobs already in the print queue. The scheduler then schedules the requested print job among the print jobs in the print queue that have print settings corresponding with the print settings of the requested print job. | 08-23-2012 |
| 20120212771 | RESOLUTION OF CONFLICTS BETWEEN PRINT JOBS AND PRINTERS IN A PRINT SHOP ENVIRONMENT - Systems and methods for identifying conflicts between the requirements of an incoming print job and the configuration of a printer that has been requested to print the job. The system receives a request to move a print job to a queue for a printer and identifies a requirement of the print job. The system analyzes a current and a scheduled configuration of the printer to determine whether the current configuration or the scheduled configuration of the printer can handle the print setting. Responsive to determining that the current and scheduled configuration of the printer cannot handle the print setting, the system analyzes configurations of at least one other printer to identify another printer having a current configuration or a scheduled configuration that can handle the print setting. Further, the system provides information identifying the other printer. | 08-23-2012 |
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| 20120017185 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically devising a processor architecture and generating a processor chip specification uniquely customized to the computer readable code which satisfies the constraints; and synthesizing the chip specification into a layout of the custom integrated circuit. | 01-19-2012 |
| 20120017187 | AUTOMATIC OPTIMAL INTEGRATED CIRCUIT GENERATOR FROM ALGORITHMS AND SPECIFICATION - Systems and methods are disclosed to automatically design a custom integrated circuit based on algorithmic process or code as input and using highly automated tools that requires virtually no human involvement is disclosed. The method includes receiving a specification of the custom integrated circuit including computer readable code and one or more constraints on the custom integrated circuit; automatically generating a computer architecture for the computer readable code that best fits the constraints; automatically determining an instruction execution sequence based on the code profile and reassigning or delaying the instruction sequence to spread operation over one or more processing blocks to reduce hot spots; continuously evaluating and optimizing one or more factors including physical implementation, and local and global area, timing, or power at an architecture level above RTL or gate-level synthesis; automatically generating a software development kit (SDK) and the associated firmware automatically to execute the computer readable code on the custom integrated circuit; automatically generating associated test suites and vectors for the computer readable code on the custom integrated circuit; and automatically synthesizing the designed architecture and generating a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
| 20120017189 | ARCHITECTURAL LEVEL POWER-AWARE OPTIMIZATION AND RISK MITIGATION - Systems and methods are disclosed to automatically synthesize a custom integrated circuit by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks to implement one or more instructions; determining an instruction execution sequence based on the code profile and reassigning the instruction sequence to spread operation to different blocks on the IC to reduce hot spots; and synthesizing the generated processor chip specification into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
| 20120017196 | SYSTEM, ARCHITECTURE AND MICRO-ARCHITECTURE (SAMA) REPRESENTATION OF AN INTEGRATED CIRCUIT - Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) design by receiving a specification of the custom IC including computer readable code to be executed by the custom IC; generating an abstraction of the IC as a system, processor architecture and micro-architecture (SAMA) representation; providing the SAMA representation to a data model having at least an architecture optimization view, a physical design view, and a software tool view; optimizing the processor architecture by iteratively updating the SAMA representation and the data model to automatically generate a processor architecture uniquely customized to the computer readable code which satisfies one or more constraints; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. The foregoing can be done with no or minimal human involvement. | 01-19-2012 |
| 20120017198 | APPLICATION DRIVEN POWER GATING - Systems and methods are disclosed to manage power in a custom integrated circuit (IC) design by receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage; automatically generating a processor architecture uniquely customized to the computer readable code, the processor architecture having one or more processing blocks and one or more power domains; determining when each processing block is needed based on the code profile and assigning each block to one of the power domains; and gating the power domains with power based on the code profile; and synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 01-19-2012 |
| 20120096420 | INTELLIGENT ARCHITECTURE CREATOR - Systems and methods are disclosed to automatically generate a processor architecture for a custom integrated circuit (IC) described by a computer readable code. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters until all timing and hardware constraints expressed as a cost function are met; and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 04-19-2012 |
| 20120185809 | ARCHITECTURE OPTIMIZER - Systems and methods are disclosed to automatically generate a custom integrated circuit (IC) described by a computer readable code or model. The IC has one or more timing and hardware constraints. The system extracts parameters defining the processor architecture from a static profile and a dynamic profile of the computer readable code; iteratively optimizes the processor architecture by changing one or more parameters of the architecture in a hierarchical manner until all timing and hardware constraints expressed as a cost function are met using an architecture optimizer (AO); and synthesizes the generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 07-19-2012 |
| 20120185820 | TOOL GENERATOR - Systems and methods are disclosed to automatically generate software development tools for an automatically generated processor architecture by: receiving a description of a target processor; automatically generating a target compiler using a compiler generator; automatically generating a target assembler using an assembler generator; automatically generating a target linker using a linker generator; automatically generating a target simulator using a simulator generator; automatically generating a target profiler using a profiler generator; iteratively generating a new processor architecture by changing one or more parameters of the processor architecture until all user constraints or requirements are met using the generated target compiler, assembler, linker, simulator, and profiler; for each new processor architecture regenerating the target compiler, assembler, linker, simulator, profiler for the new processor architecture; and synthesizing an optimal generated processor architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication. | 07-19-2012 |
