Patent application number | Description | Published |
20130336049 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array - The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data. | 12-19-2013 |
20130336050 | Processors and Systems with Read-Qualified-on-Startup Phase-Change Memory - Systems in which PCM is used, including memory systems, as well as methods for operating such systems. A test of PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read PCM. This can be used to accelerate availability of memory states residing in PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 12-19-2013 |
20130336051 | MULTIBIT MEMORY WITH READ VOLTAGE QUALIFICATION AT STARTUP - Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 12-19-2013 |
20130336052 | Processors and Systems With Read Voltage Qualification of Multibit Phase-Change Memory - Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 12-19-2013 |
20140071748 | Systems, Methods, and Devices with Write Optimization in Phase Change Memory - Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states. | 03-13-2014 |
20140140128 | Processors and Systems with Divided-Down Phase Change Memory Read Voltages - Methods and systems for fast, low power PCM memory using a bitline precharge scheme in which unselected bitlines are driven to predetermined voltages and a selected bitline is set to ground, such that when selected and unselected bitlines are shorted together, the selected bitline is charged to a PCM sense voltage. Inventive methods and systems do not require a precharge voltage regulator to drive selected bitlines to a sense voltage. | 05-22-2014 |
20140146602 | Divided-Down Read Voltage in Phase Change Memory Cells - Methods and systems for fast, low power PCM memory using a bitline precharge scheme in which unselected bitlines are driven to predetermined voltages and a selected bitline is set to ground, such that when selected and unselected bitlines are shorted together, the selected bitline is charged to a PCM sense voltage. Inventive methods and systems do not require a precharge voltage regulator to drive selected bitlines to a sense voltage. | 05-29-2014 |
20140204666 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array - The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data. | 07-24-2014 |
20140204667 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array - The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data. | 07-24-2014 |
20140204668 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array - The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data. | 07-24-2014 |
20140211554 | Systems, Methods, and Devices with Write Optimization in Phase Change Memory - Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states. | 07-31-2014 |
20140211555 | Systems, Methods, and Devices with Write Optimization in Phase Change Memory - Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states. | 07-31-2014 |
20140211556 | Systems, Methods, and Devices with Write Optimization in Phase Change Memory - Methods and systems for phase change memories and arrays with improved write characteristics. If a data word can be more efficiently written by e.g. exchanging SETs and RESETs, it is written as such on the fly, and e.g. a bit of overhead is written to indicate the transformation. This has a surprising synergy with phase change memory as SET operations usually take longer and consume more power than do RESET operations. In one sample embodiment of multilevel phase change memory, states intermediate between SET and RESET can be even less desirable to write than SETs, as they take more precision than do the extreme states of SET and RESET, so that a desirable transformation can be to exchange intermediate states for extreme states. | 07-31-2014 |
20140321200 | PHASE CHANGE MEMORY WITH FLEXIBLE TIME-BASED CELL DECODING - Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing. | 10-30-2014 |
20150078076 | PHASE CHANGE MEMORY WITH FLEXIBLE TIME-BASED CELL DECODING - Methods and systems for time-based cell decoding for PCM memory. Generally, the higher the PCM element resistance, the longer it takes for a read output to change state. PCM memory output is determined using differentiated timings of read outputs changing state, rather than differentiated values of read outputs. In some single-bit single-ended sensing embodiments, a reference, with resistance between the resistances corresponding to a pair of adjacent logical states, is stored in multiple reference cells; a “vote” unit emits a clock signal when a majority of the reference cell read outputs transition at the vote unit. Timing units produce different binary outputs depending on whether a data read output or the clock signal changes state first at the timing unit. Time-based decoding provides advantages including improved temperature and drift resilience, improved state discrimination, improved reliability of multibit PCM, and fast and reliable sensing. | 03-19-2015 |