| Patent application number | Description | Published |
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| 20100132993 | WIRING BOARD AND ELECTRONIC COMPONENT DEVICE - A wiring board includes a wiring forming region in which a plurality of wiring layers are stacked while sandwiching insulating layers, an outer periphery region which is arranged around the wiring forming region and in which a reinforcing pattern is formed in the same layer as each of the wiring layers. An area ratio of the reinforcing pattern to the outer periphery region and an area ratio of the wiring layer to the wiring forming region are substantially the same in each of the layers, and the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective. | 06-03-2010 |
| 20110034022 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD - A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board ( | 02-10-2011 |
| 20110169164 | WIRING SUBSTRATE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE - A disclosed wiring substrate includes an insulating layer, a recess formed on a surface of the insulating layer, and an alignment mark formed inside of the recess, wherein a face of the alignment mark is roughened, recessed from the surface of the insulating layer, and exposed from the recess. | 07-14-2011 |
| 20110297425 | WIRING SUBSTRATE AND MANUFACTURING METHOD THEREOF - A wiring substrate includes a plurality of insulating layers; and a plurality of wiring layers being alternately laminated, wherein an opening portion is formed in an outermost insulating layer to expose a part of the outermost wiring layer to an outside, a cross-sectional shape of a sidewall of the opening portion is concaved and curved, and the outermost wiring layer has a recess on a side exposed to the outside. | 12-08-2011 |
| 20110304016 | WIRING BOARD, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - A wiring board includes a structure in which a plurality of wiring layers are stacked with insulating layers interposed therebetween, a plurality of pads for mounting an electronic component, the pads being formed on an outermost insulating layer on one surface side of the structure and exposed to the surface of the outermost insulating layer, and a recessed portion formed at a place corresponding to a mounting area for the electronic component. The recessed portion is formed in the outermost insulating layer at an area between the pads to which electrode terminals of the electronic component to be mounted are to be connected, respectively. | 12-15-2011 |
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| 20080204364 | Color display device and color display method - The color display device includes a colored light generation unit for repetitively generating a plurality of colored lights in a time sequence with a predetermined frequency, and an image generation unit for processing said plurality of colored lights, so as to generate an image corresponding to each of the plurality of colored lights generated in a time sequence. The said predetermined frequency is 180 Hz or more. | 08-28-2008 |
| 20080204365 | Color display device and color display method - The color display device includes a colored light generation unit for repetitively generating a plurality of colored lights in a time sequence with a predetermined frequency, and an image generation unit for processing said plurality of colored lights, so as to generate an image corresponding to each of the plurality of colored lights generated in a time sequence. The said predetermined frequency is 180 Hz or more. | 08-28-2008 |
| 20090174724 | Color display device and color display method - The color display device includes a colored light generation unit for repetitively generating a plurality of colored lights in a time sequence with a predetermined frequency, and an image generation unit for processing said plurality of colored lights, so as to generate an image corresponding to each of the plurality of colored lights generated in a time sequence. The said predetermined frequency is 180 Hz or more. | 07-09-2009 |
| 20100097298 | COLOR DISPLAY DEVICE AND COLOR DISPLAY METHOD - The color display device includes a colored light generation unit for repetitively generating a plurality of colored lights in a time sequence with a predetermined frequency, and an image generation unit for processing said plurality of colored lights, so as to generate an image corresponding to each of the plurality of colored lights generated in a time sequence. The said predetermined frequency is 180 Hz or more. | 04-22-2010 |
| 20110001688 | COLOR DISPLAY DEVICE AND COLOR DISPLAY METHOD - The color display device includes a colored light generation unit for repetitively generating a plurality of colored lights in a time sequence with a predetermined frequency, and an image generation unit for processing said plurality of colored lights, so as to generate an image corresponding to each of the plurality of colored lights generated in a time sequence. The said predetermined frequency is 180 Hz or more. | 01-06-2011 |
| 20110221796 | COLOR DISPLAY DEVICE AND COLOR DISPLAY METHOD - The color display device includes a colored light generation unit for repetitively generating a plurality of colored lights in a time sequence with a predetermined frequency, and an image generation unit for processing said plurality of colored lights, so as to generate an image corresponding to each of the plurality of colored lights generated in a time sequence. The said predetermined frequency is 180 Hz or more. | 09-15-2011 |
| Patent application number | Description | Published |
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| 20080245549 | WIRING BOARD AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a wiring board, the method includes: (i) forming a plurality of conductive patterns to come into contact with a support plate; (ii) forming a resin layer to cover the plurality of conductive patterns and to come into contact with the support plate; (iii) forming another conductive pattern connected to at least one of the plurality of conductive patterns; and (iv) removing the support plate. A first area of the support plate coming into contact with at least one of the plurality of conductive patterns in step (i) is different in surface roughness from a second area of the support plate coming into contact with the resin layer in step (ii). | 10-09-2008 |
| 20080258300 | WIRING BOARD MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WIRING BOARD - A semiconductor device | 10-23-2008 |
| 20080265398 | SUBSTRATE WITH PIN, WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate with pins comprises pins, and a holding substrate in which through holes to which the pins are attached are formed. Head parts of the pins are arranged in the through holes. The pins are attached by pressing the head parts in the through holes. | 10-30-2008 |
| 20090126982 | WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A wiring board | 05-21-2009 |
| 20090133910 | PRODUCTION METHOD OF MULTILAYER PRINTED WIRING BOARD AND MULTILAYER PRINTED WIRING BOARD - Multilayer printed wiring boards may be prepared by forming a via hole by laser irradiation in insulating layer formed by a prepreg, comprised of a glass cloth impregnated with a thermosetting resin composition, and subjecting the via hole to a glass etching treatment with a glass etching solution and then to a desmear treatment with an oxidizing agent solution. By such a process, etch back phenomenon and excessive protrusion of glass cloth from the wall surface of a via hole can be sufficiently suppressed, and a highly reliable via can be formed. Particularly, a highly reliable via can be formed in a small via hole having a top diameter of 75 μm or below. | 05-28-2009 |
| 20100263923 | WIRING SUBSTRATE HAVING COLUMNAR PROTRUDING PART - A method of making a wiring substrate includes forming a first metal layer on a surface of a support member, the first metal layer having at least one columnar through hole that exposes the surface of the support member, forming a columnar metal layer that fills the columnar through hole, forming an insulating layer on the columnar metal layer and on the first metal layer, forming an interconnection layer on a first surface of the insulating layer such that the interconnection layer is electrically connected to the columnar metal layer through the insulating layer, and forming a protruding part including at least part of the columnar metal layer by removing at least the support member and the first metal layer, the protruding part protruding from a second surface of the insulating layer opposite the first surface and serving as at least part of a connection terminal of the wiring substrate. | 10-21-2010 |
| 20110139502 | WIRING BOARD MANUFACTURING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WIRING BOARD - A semiconductor device | 06-16-2011 |
| 20110286189 | METHOD OF FABRICATING WIRING BOARD AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer. | 11-24-2011 |
| 20120006591 | Wiring Substrate and Method for Manufacturing Wiring Substrate - A wiring substrate that prevents the occurrence of delamination near an interface between an insulation layer and an electrode pad, which is formed in a recess of the insulation layer. An adjustment layer is formed in an opening in a resist, which is applied to a support body, to adjust the shape of the electrode pad. The adjustment layer includes a flat surface, which is substantially parallel to the support body, and an inclined surface, which extends from a rim of the flat surface toward the support body and to the side wall of the opening. A pad body of the electrode pad and an insulation layer including a wire is formed on the adjustment layer. The support body and adjustment layer are etched to expose the pad body. | 01-12-2012 |
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| 20090187965 | ELECTRONIC APPARATUS, METHOD FOR CONTROLLING FUNCTIONS OF THE APPARATUS AND SERVER - An electronic apparatus, having functions on which use limitations can be imposed, in which a variety of functions are loaded on the electronic apparatus by hardware circuitry or by computer programs. Use of a certain function(s) is limited by setting a function limiting flag to “1”, provided that an other function(s) are usable within a period of a preset number of days of possible test use. An application is made from the apparatus to a key issuing source for purchasing usable functions. The key issuing source then issues a limitation removing key. The limitation removing key may be acquired from the key issuing source by a mobile phone terminal and transmitted to the apparatus by infrared ray communication. The apparatus rewrites the function limiting flag by this limitation removing key. If the number of days of actual test use has reached the number of days of possible test use, the CPU of the apparatus does not carry out the function(s) the function limiting flag of which is “1”. | 07-23-2009 |
| 20100034392 | ELECTRONIC APPARATUS, METHOD FOR CONTROLLING FUNCTIONS OF THE APPARATUS AND SERVER - An electronic apparatus, having functions on which use limitations can be imposed, in which a variety of functions are loaded on the electronic apparatus by hardware circuitry or by computer programs. Use of a certain function(s) is limited by setting a function limiting flag to “1”, provided that an other function(s) are usable within a period of a preset number of days of possible test use. An application is made from the apparatus to a key issuing source for purchasing usable functions. The key issuing source then issues a limitation removing key. The limitation removing key may be acquired from the key issuing source by a mobile phone terminal and transmitted to the apparatus by infrared ray communication. The apparatus rewrites the function limiting flag by this limitation removing key. If the number of days of actual test use has reached the number of days of possible test use, the CPU of the apparatus does not carry out the function(s) the function limiting flag of which is “1”. | 02-11-2010 |
| 20110113151 | CONTENT DISPLAY-PLAYBACK SYSTEM, CONTENT DISPLAY-PLAYBACK METHOD, RECORDING MEDIUM HAVING CONTENT DISPLAY-PLAYBACK PROGRAM RECORDED THEREON, AND OPERATION CONTROL APPARATUS - A content display-playback system includes at least one server that distributes audio-visual content via streaming, and at least one client that plays back, by streaming, the content distributed via streaming from the server, and the server and client are connected. The client beforehand makes settings regarding a client operation to be performed for submitting a streaming distribution request to the server to perform playback by streaming | 05-12-2011 |
| 20120057725 | CONTROL TERMINAL APPARATUS AND CONTROL METHOD - A control terminal apparatus includes a transmission unit transmitting a control signal to audio output apparatuses, a display unit, an operation detector detecting an operation associated with display content, and a controller displaying individual volume setting sections which correspond to the audio output apparatuses and which include operation members performing variable operations of volume settings while volume setting states are displayed, displaying a master volume setting section including an operation member performing collective variable operation while the volume balance of the audio output apparatuses is maintained, executing clear display of a setting changeable range in which the volume balance is maintained in the master volume setting section, generating, when the operation detector detects an operation performed on one of the individual volume setting sections or the master volume setting section, a control signal corresponding to content of the operation, and causing the transmission unit to transmit the control signal. | 03-08-2012 |
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| 20080225133 | CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics - An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components. | 09-18-2008 |
| 20080293818 | Regulator of Physiological Function of Ghrelin and Use Thereof - A regulator for regulating physiological functions, such as activity of increasing an intracellular calcium ion concentration, activity of promoting growth hormone secretion, activity of promoting eating, regulatory activity relating to fat accumulation, activity of ameliorating heart function and activity of stimulating gastric acid secretion, of ghrelin, which regulator comprises a fatty acid of carbon number 2-35 or its derivative, and use thereof. | 11-27-2008 |
| 20090002536 | Biasing scheme for large format CMOS active pixel sensors - An image sensor includes circuitry compensating for voltage drops in a V | 01-01-2009 |
| 20090180015 | WIDE DYNAMIC RANGE PINNED PHOTODIODE ACTIVE PIXEL SENSOR (APS) - An image apparatus and method is disclosed for extending the dynamic range of an image sensor. A first linear pixel circuit produces a first pixel output signal based on charge integration by a first photo-conversion device over a first integration period. A second linear pixel circuit produces a second pixel output signal based on charge integration by a second photo-conversion device over a second integration period, where the second integration period is shorter than the first integration period. A sample-and-hold circuit captures signals representing the first and second pixel output signals. | 07-16-2009 |
| 20090200455 | CMOS APS WITH STACKED AVALANCHE MULTIPLICATION LAYER AND LOW VOLTAGE READOUT ELECTRONICS - An image sensor includes a pixel having a protection circuit connected to a charge multiplying photoconversion layer. The protection circuit prevents the pixel circuit from breaking down when the voltage in the pixel circuit reaches the operating voltage applied to the charge multiplying photoconversion layer in response to the image sensor being exposed to a strong light. The protection circuit causes additional voltage entering the pixel circuit from the charge multiplying photoconversion layer over a predetermined threshold voltage level to be dissipated from the storage node and any downstream components. | 08-13-2009 |
| 20090303368 | IMAGE SENSOR WITH ON-CHIP SEMI-COLUMN-PARALLEL PIPELINE ADCS - An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures. | 12-10-2009 |
