Patent application number | Description | Published |
20110085397 | Semiconductor device and information processing system including the same - A semiconductor device includes plural core chips and an interface chip that controls the plural core chips. Each of the plural core chips includes a layer address generating circuit that generates a second chip address by incrementing a value of a first chip address and a layer address comparing circuit that compares a third chip address supplied from the interface chip and the second chip address, and activates a chip selection signal when the third chip address and the second chip address are matched with each other. When a non-used chip signal is in an inactivated state, the layer address generating circuit supplies the second chip address to another core chip, and when the non-used chip signal is in an activated state, the layer address generating circuit supplies the first chip address to another core chip without a change. | 04-14-2011 |
20110087835 | Semiconductor memory device and data processing system - To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation. | 04-14-2011 |
20110305057 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE - In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened. | 12-15-2011 |
20120114086 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips. | 05-10-2012 |
20120182822 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated. | 07-19-2012 |
20120195090 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - Such a device is disclosed that includes first and second chips stacked to each other, and a third chip controlling the first and second chips, stacked on the first and second chips, and including first, second and third output circuits. The first output circuit supplies a first command signal to the first chip. The second output circuit supplies the first command signal to the second chip. The third output circuit supplies a second command signal to the first and second chips. | 08-02-2012 |
20140078848 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE - In one embodiment, a semiconductor memory device receives a refresh command and address information, and supplies a refresh control signal and the address information in common to core chips. Each of the core chips includes a layer-address comparison circuit that determines whether the address information assigns an own core chip, and a refresh control circuit that refreshes an own memory cell based on the refresh control signal when the address information assigns the own core chip. With this arrangement, a memory capacity of a chip that is refreshed by a refresh command for one time is reduced, and therefore a shortest issuing interval of a refresh command can be shortened. | 03-20-2014 |
20140177367 | SEMICONDUCTOR DEVICE INCLUDING PLURAL CHIPS STACKED TO EACH OTHER - A device includes a plurality of Dynamic Random Access Memory (DRAM) chips in a stacked configuration connected by through silicon vias (TSVs), and each of the plurality of DRAM chips being configured to provide a local bank active signal to indicate when any one of a plurality of banks on a respective one of the plurality of DRAM chips is active, and local bank active signals from the plurality of DRAM chips being supplied through TSVs of intervening ones of the plurality of DRAM chips to a lowermost one of the plurality of DRAM chips. | 06-26-2014 |
20140247684 | Semiconductor Device - A semiconductor device includes: an interface chip including a read timing control circuit that outputs, in response to a command signal and a clock signal supplied from the outside, a plurality of read control signals that are each in synchronization with the clock signal and have different timings; and core chips including a plurality of internal circuits that are stacked on the interface chip and each perform an operation indicated by the command signal in synchronization with the read control signals. According to the present invention, it is unnecessary to control latency in the core chips and therefore to supply the clock signal to the core chips. | 09-04-2014 |
20140376321 | SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM - To include a plurality of core chips to which different pieces of chip information from each other are given in advance. A first refresh command is divided into a plurality of second refresh commands having different timings from each other, and a refresh operation is performed on a core chip for which a count value of the second refresh commands and at least a portion of the chip information match each other. With this configuration, even when the second refresh command is commonly supplied to a plurality of core chips, it is possible to shift a timing for the refresh operation in each of the core chips. Therefore, it is possible to reduce a peak current at the time of the refresh operation. | 12-25-2014 |