| Patent application number | Description | Published |
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| 20090106482 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT - In one or more embodiments, a memory device is disclosed as having an adjustable programming window having a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences factors such as erase/program cycles that change the program window. The initial programming window is determined prior to an initial erase/program cycle. The programming levels are then moved as the programming window changes, such that the plurality of programmable levels still remain within the program window and are tracked with the program window changes. | 04-23-2009 |
| 20090129146 | MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE - In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations. | 05-21-2009 |
| 20090129153 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 05-21-2009 |
| 20090231926 | ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations. | 09-17-2009 |
| 20100039864 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-18-2010 |
| 20100091565 | M+N BIT PROGRAMMING AND M+L BIT READ FOR M BIT MEMORY CELLS - A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory. | 04-15-2010 |
| 20100246271 | ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE - Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read circuit stores a read threshold voltage that was read from a selected memory cell. The verify circuit stores a target threshold voltage that is compared to the read threshold voltage to generate an inhibit signal when the target and read threshold voltages are substantially equal. The reference circuit stores a reference threshold voltage that can be used to translate the read threshold voltage to compensate for a transistor voltage drop and/or temperature variations. | 09-30-2010 |
| 20110032761 | METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE - Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification. | 02-10-2011 |
| 20110058413 | MITIGATION OF DATA CORRUPTION FROM BACK PATTERN AND PROGRAM DISTURB IN A NON-VOLATILE MEMORY DEVICE - In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program disturb in memory cells. Original data to be programmed is adjusted prior to an initial programming operation of the memory cells. The original data is then programmed into the memory cells in another programming operation. In an alternate embodiment, a read adjustment weight data value is associated with each series string of memory cells. The weight data value is used to compensate data read during an initial word line read. The weight data value is updated after each read and read adjustment such that the adjusted weight data value is used on the subsequent read operations. | 03-10-2011 |
