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Jung, Icheon-Si
Boo Ho Jung, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120061739 | METHOD FOR FABRICATING CAPACITOR AND SEMICONDUCTOR DEVICE USING THE SAME - Provided are a method for fabricating a capacitor and a semiconductor device using the same. The semiconductor device includes a MOS transistor capacitor, first and second plate capacitors, and a metal interconnection. The MOS transistor capacitor is arranged between a power supply and a ground. The first and second plate capacitors are arranged between the power supply and the ground. The metal interconnection is configured to connect the first and second plate capacitors. | 03-15-2012 |
Dongjin Jung, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090166835 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERPOSER - An integrated circuit package system including: providing a base substrate; coupling a base integrated circuit on the base substrate; forming a double side molded interposer unit over the base integrated circuit including: providing an interposer substrate having an interposer top and an interposer bottom, mounting a first integrated circuit to the interposer bottom and electrically connected thereto, mounting a second integrated circuit to the interposer top and electrically connected thereto, and molding a first chip cover on the first integrated circuit and a second chip cover on the second integrated circuit; and coupling an external component to the double side molded interposer unit. | 07-02-2009 |
| 20090236718 | PACKAGE-ON-PACKAGE SYSTEM WITH INTERNAL STACKING MODULE INTERPOSER - A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors. | 09-24-2009 |
| 20100038781 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity. | 02-18-2010 |
| 20100237482 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LAYERED PACKAGING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace. | 09-23-2010 |
| 20110272807 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity. | 11-10-2011 |
Ha Chang Jung, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20120087179 | MAGNETO-RESISTANCE ELEMENT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A magneto-resistance element is provided. The magneto-resistance element includes an underlying layer including a main metal selected from electrically conductive metals and an auxiliary metal selected from transition metals, a first magnetic layer stacked on the underlying layer, an insulation layer stacked on the first magnetic layer, and a second magnetic layer stacked on the insulation layer. | 04-12-2012 |
Hun Sam Jung, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090051397 | Clock pulse generating circuit - A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator. | 02-26-2009 |
| 20100109737 | Clock pulse generating circuit - A clock pulse generating circuit includes a pulse generator, a clock regulator, and a pre-driver. The pulse generator is configured to vary pulse widths of a rising clock signal and a falling clock signal. The clock regulator is configured to regulate output signals of the pulse generator to prevent an overlap and a duty drop of the output signals of the pulse generator. The pre-driver is configured to output data driving signals according to output signals of the clock regulator. | 05-06-2010 |
Sun-Hwa Jung, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090218696 | SEMICONDUCTOR DEVICE INCLUDING A PADDING UNIT - A semiconductor device includes bit lines formed over a substrate and a padding unit formed over the bit lines. The padding unit includes stacked padding layers. A lower padding layer is formed between the bit lines and an upper padding layer. The upper layer as a slit formed therein. The lower padding layer prevents damage to the bit lines due to plasma gas entering through the slit. | 09-03-2009 |
Yong Soon Jung, Icheon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20090221126 | Method of Fabricating Capacitor of Semiconductor Device - Disclosed herein is a method of fabricating a capacitor of a semiconductor device that includes sequentially forming an interlayer insulating film defining a contact plug, a lower electrode oxide film, and a hard mask film over a semiconductor substrate; etching the hard mask film with a mask comprising a dummy pattern and a cell pattern to form a hard mask pattern wherein a first trench is formed in a dummy pattern region and a second trench is formed in a cell pattern region; forming a capping film that buries the first trench; and etching the lower electrode oxide film with the capping film and the hard mask pattern as a mask to form a lower electrode trench that exposes the contact plug. | 09-03-2009 |