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Jung-Hyeon

Jung-Hyeon Kim, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20090065175FIN-TYPE HEAT SINK FOR ELECTRONIC COMPONENT - One embodiment exemplarily described herein can be generally characterized as a heat sink for an electronic component. The heat sink may include a main body thermally contactable to an electronic component; at least one fin thermally contacted with the main body; and a confining member. The at least one fin and the confining member may be cooperatively engaged such that the at least one fin is moveable between a first position relative to a longitudinal axis of the main body and a second position relative to the longitudinal axis of the relative to the main body.03-12-2009
20090245079OPTICAL RECORDING MEDIUM HAVING SUPER-RESOLUTION STRUCTURE FOR IMPROVEMENT OF REPRODUCING STABILITY AND NOISE CHARACTERISTIC IN LOW FREQUENCY BAND - A super-resolution optical recording medium includes a reflective layer formed on a substrate, a recording layer for recording information thereon, a super-resolution layer made of a chalcogenide semiconductor material, and a first and a second dielectric layers laminated on upper and lower surfaces of the super-resolution layer. The recording layer is made of a material that has a decomposition temperature higher than an information reproduction temperature and does not form bubble recording marks during recording, and the super-resolution layer contains one or more elements selected from the group consisting of nitrogen, oxygen, carbon, and boron.10-01-2009
20110081762Methods of fabricating non-volatile memory devices with discrete resistive memory material regions - A semiconductor memory device includes a first conductive line on a semiconductor substrate, an interlayer insulating layer on the first conductive line, a second conductive line on the interlayer insulating layer, and a memory cell in an hole through the interlayer insulating layer wherein the first and second conductive lines cross, the memory cell including a discrete resistive memory material region disposed in the hole and electrically connected between the first and second conductive lines. The resistive memory material region may be substantially contained within the hole. In some embodiments, contact between the resistive memory material region and the interlayer insulating layer is substantially limited to sidewalls of the interlayer insulating layer in the hole.04-07-2011
20110085289HINGE UNIT AND PORTABLE COMPUTER HAVING THE SAME - Disclosed are a hinge unit which couples a first member and a second member, the hinge unit including: a conic shaft which is coupled to the first member, and comprises a hinge pivot, a conic unit of a truncated cone shape, the radius of which is extended in an end area of the hinge pivot, and a first rocking unit formed to an outer surface of the conic unit; and a conic sleeve which is coupled to the second member, and comprises a sleeve main body formed with a conic accommodating unit having a shape corresponding to the conic unit in an inner part of the conic accommodating unit, and a second rocking unit formed to an inner surface of the conic accommodating unit to be coupled with the first rocking unit.04-14-2011
20110142239SECURITY PROTECTED NON-ACCESS STRATUM PROTOCOL OPERATION SUPPORTING METHOD IN A MOBILE TELECOMMUNICATION SYSTEM - The present invention relates to a method and system for the management of the mobility, the management of an idle mode, the registration management (management of attachment and detachment), and the location management (management of tracking area) of a terminal by using a non-access stratum (i.e., network stratum, hereinafter referred to as “NAS”) in a mobile telecommunication network. To this end, the method for the management of mobility, the management of an idle mode, the registration management, and the location management of a terminal by using a NAS protocol, i.e., messages, according to an embodiment of the present invention, includes a terminal (hereinafter, referred to as “UE”) and a mobility management entity (hereinafter, referred to as “MME”), and addresses to a method for efficiently processing security protected NAS messages if received messages are security protected NAS messages, in a case of sending or receiving messages serving as EMM (EPS Mobility Management) messages, i.e., mobility management messages, in a network such as an EPS (Evolved Packet System) of 3GPP, when the terminal performs handover in an active mode, performs location management in an idle mode, and registers to a network, thereby achieving improved efficiency in the mobility management, the position management, and the registration management of a terminal.06-16-2011

Patent applications by Jung-Hyeon Kim, Gyeonggi-Do KR

Jung-Hyeon Kim, Seoul KR

Patent application numberDescriptionPublished
20100232124SUPER CAPACITOR CASING AND SUPERCAPACITOR EMBEDDED DEVICE - A casing to support a solid state device SSD therein and super capacitors therein to be electronically connected together.09-16-2010

Jung-Hyeon Kim, Hwaseong-Si, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20100105201SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor package, a circuit board and an interval maintaining member. The semiconductor package has a body and a lead protruded from the body. The circuit board has a first land electrically connected to the lead. The interval maintaining member is interposed between the circuit board and the body. The interval maintaining member maintains an interval between the lead and the first land. Thus, an interval between the lead and the land is uniformly maintained, so that a thermal and/or mechanical reliability of the semiconductor device is improved.04-29-2010

Jung-Hyeon Lee, Gyeonggi-Do KR

Patent application numberDescriptionPublished
20080230929OVERLAY MARK OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE OVERLAY MARK - Provided are an overlay mark of a semiconductor device and a semiconductor device including the overlay mark. The overlay mark includes: reference marks formed in rectangular shapes comprising sides in which fine patterns are formed; and comparison marks formed as rectangular shapes which are smaller than the rectangular shapes of the reference marks and formed of fine patterns, wherein the number of comparison marks is equal to the number of reference marks, wherein the reference marks and the comparison marks are formed on different thin films formed on a semiconductor substrate to be used to inspect alignment states of the different thin films, and the overlay mark reflects an effect of aberration of patterns of memory cells through the fine patterns during a calculation of MR (mis-registration).09-25-2008
20090274980METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE BY USING DOUBLE PATTERNING PROCESS WHICH USES ACID DIFFUSION - A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.11-05-2009

Patent applications by Jung-Hyeon Lee, Gyeonggi-Do KR

Jung-Hyeon Lee, Yongin-Si KR

Patent application numberDescriptionPublished
20080280381Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key - In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.11-13-2008

Patent applications by Jung-Hyeon Lee, Yongin-Si KR