Patent application number | Description | Published |
20100194457 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A delay locked loop circuit includes: a delay locked loop block receiving an external clock and generating a delay locked internal clock; a duty cycle correcting block connected to the delay locked loop block and correcting the duty cycle of the internal clock; and an error detecting unit comparing the voltages of first and second pumping output nodes of the duty cycle correcting block to detect an operation error of the duty cycle correcting block. | 08-05-2010 |
20110109344 | Semiconductor devices having on-die termination structures for reducing current consumption and termination methods performed in the semiconductor devices - Example embodiments disclose a semiconductor device having an on-die termination (ODT) structure that reduces current consumption, and a termination method performed in the semiconductor device. The semiconductor device includes a calibration circuit for generating calibration codes in response to a reference voltage and a voltage of a calibration terminal connected to an external resistor and an on-die termination device for controlling a termination resistance of a data input/output pad in response to the calibration codes and an on-die termination control signal. The termination resistance of the data input/output pad is greater than a resistance of the calibration terminal. | 05-12-2011 |
20110116330 | SEMICONDUCTOR DEVICE HAVING ADDITIVE LATENCY - A semiconductor device receives a command corresponding to a memory access operation and performs the memory access operation after an additive latency period. The additive latency period begins when the command is received. The semiconductor device comprises a phase controller for controlling a phase of a clock signal and outputting a phase-controlled clock signal, and a controller for generating and outputting a control signal for enabling the phase controller that is disabled, at a predetermined time in the additive latency period. | 05-19-2011 |
20110153939 | SEMICONDUCTOR DEVICE, CONTROLLER ASSOCIATED THEREWITH, SYSTEM INCLUDING THE SAME, AND METHODS OF OPERATION - In one embodiment, the semiconductor device includes a data control unit configured to selectively process data for writing to a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group of processing functions including at least three processing functions. The enabled processing function may be performed based on a signal received over a single pin associated with the group of processing functions. In another embodiment, the semiconductor device includes a data control unit configured to process data read from a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a read operation. Here, the group of processing functions including at least two processing functions. | 06-23-2011 |
20110164462 | DELAY-LOCKED-LOOP CIRCUIT, SEMICONDUCTOR DEVICE AND MEMORY SYSTEM HAVING THE DELAY-LOCKED-LOOP CIRCUIT - A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency. | 07-07-2011 |
20130069689 | Method For Operating Memory Device And Apparatuses Performing The Method - According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal. | 03-21-2013 |
20130120043 | DELAY-LOCKED-LOOP CIRCUIT - A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency. | 05-16-2013 |
20130198587 | MEMORY BUFFER PERFORMING ERROR CORRECTION CODING (ECC) - A memory system includes a semiconductor memory device, a memory controller for controlling the semiconductor memory device, and a memory buffer connected between the semiconductor memory device and the memory controller. The memory buffer is configured to perform error correction coding (ECC) on first data that is received from the memory controller to be stored in the semiconductor memory device and to perform ECC on second data read from the semiconductor memory device. | 08-01-2013 |
20130223171 | Semiconductor Device Capable of Rescuing Defective Characteristics Occurring After Packaging - A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source. | 08-29-2013 |
20130254495 | MEMORY SYSTEM - A memory system includes a memory controller, and first through fourth memory modules. The first memory module is directly connected to the memory controller through a first memory bus and exchanges first data with the memory controller through the first memory bus. The second memory module is directly connected to the memory controller through a second memory bus and exchanges second data with the memory controller through the second memory bus. The third memory module is connected to the first memory module through a third memory bus and exchanges the first data with the memory controller through the first and third memory buses. The fourth memory module is connected to the second memory module through a fourth memory bus and exchanges the second data with the memory controller through the second and fourth memory buses. | 09-26-2013 |
20140152340 | OPERATING METHOD OF INPUT/OUTPUT INTERFACE - A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal. | 06-05-2014 |
20140169119 | MEMORY SYSTEM HAVING DELAY-LOCKED-LOOP CIRCUIT - A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency. | 06-19-2014 |
20140189227 | MEMORY DEVICE AND A MEMORY MODULE HAVING THE SAME - A memory device is provided. The memory device includes a plurality of memory chips, and a buffer chip connected to the plurality of memory chips. The plurality of memory chips and the buffer chip are disposed in a stack. A first input/output (IO) port of the buffer chip is connected in series to an external device, and a second IO port of the buffer chip is connected in parallel to IO ports of each of the plurality of memory chips. | 07-03-2014 |
20140203457 | STACKED DIE PACKAGE, SYSTEM INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME - A stacked die package includes a package substrate, a first die mounted on the package substrate and electrically connected to the package substrate, a second die electrically connected to the package substrate, and an interposer mounted on the package substrate and including a plurality of vertical electrical connection means electrically connecting the package substrate to the second die. At least part of the first die is disposed between the second die and the package substrate in a vertical direction. | 07-24-2014 |
20140270785 | ELECTRO-PHOTONIC MEMORY SYSTEM - An electro-photonic memory system includes a semiconductor memory device for storing data by receiving a first electrical signal, a memory controller for generating a second electrical signal to control the semiconductor memory device, an electrical-to-optical converter for receiving the second electrical signal from the memory controller and converting the second electrical signal into an optical signal, the electrical-to-optical converter separate from the memory controller, and an optical-to-electrical converter for receiving the optical signal from the electrical-to-optical converter and converting the optical signal into the first electrical signal. | 09-18-2014 |
20140313847 | CLOCK SYNCHRONIZATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING CLOCK SYNCHRONIZATION CIRCUIT - A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state | 10-23-2014 |
20150067448 | METHOD OF OPERATING MEMORY DEVICE AND METHODS OF WRITING AND READING DATA IN MEMORY DEVICE - In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word. | 03-05-2015 |