| Patent application number | Description | Published |
|---|
| 20090015290 | ON-DIE TERMINATION DEVICE TO COMPENSATE FOR A CHANGE IN AN EXTERNAL VOLTAGE - An on-die termination (ODT) control in a semiconductor memory device compensates for a change in an external voltage. The on-die termination device includes a voltage comparator that compares an external voltage to a set internal reference voltage. The compared values are sent to a controller that controls an on-die termination impedance value according to the output signal from the voltage comparator. Based on the output of the controller, the present invention spontaneously controls an on-die termination resistance value according to the change in the external voltage without degrading device characteristics during high-speed operation. | 01-15-2009 |
| 20090102510 | CONTROL CIRCUIT FOR CONTROLLING ON-DIE TERMINATION IMPEDANCE - The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal. | 04-23-2009 |
| 20090230376 | RESISTIVE MEMORY DEVICES - Provided is a resistive memory device that can be integrated with a high integration density and method of forming the same. In an embodiment, a bit line is formed of copper using a damascene technique, and when the copper bit line, a copper stud may be formed around the copper bit line | 09-17-2009 |
| 20090242866 | Phase change memory device and method of fabricating the same - A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance. | 10-01-2009 |
| 20090267637 | DEVICE AND METHOD FOR TESTING A RESISTANCE VALUE OF ON-DIE-TERMINATION DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A device and a method for testing a resistance value of an on-die-termination (ODT) device and a semiconductor device having the same are presented. The device can include a comparator, a storage unit and and an output unit. When in an ODT test operation mode, the comparator compares a reference voltage against an input data input to a pad to determine the resistance value of the ODT device and outputs a determination data on the resistance value of the ODT device corresponding to the determination results. The storage unit stores the output of the comparator in synchronization with a clock signal. When in the ODT test operation mode, the output unit outputs the determination data on the resistance value of the ODT device stored in the storage unit to the pad. Thereby not only is the device configured to determine whether or not a defect of the resistance value of the ODT device exists but the device and the method are able to achieve this task in a substantially shorter testing time period. | 10-29-2009 |
| 20100045340 | CONTROL CIRCUIT FOR CONTROLLING ON-DIE TERMINATION IMPEDANCE - The present invention relates to an ODT control circuit which is controlled in synchronization with an external clock during power-down mode. An ODT control circuit according to the present invention includes a clock control circuit which receives a synchronized internal clock signal and a DLL clock signal, and selects either one of the internal clock signal or the DLL clock signal according to the power mode to output a plurality of delayed clock signals; and an ODT control signal generation circuit which receives an ODT command, and controls the ODT command with the internal clock signal and a plurality of the delayed clock signals to generate and output an ODT control signal. According to the present invention, an ODT control signal for controlling an on-die termination resistor is synchronized with an external clock even during power-down mode, thereby more effectively controlling the ODT control signal. | 02-25-2010 |
| 20100200833 | SEMICONDUCTOR DEVICE INCLUDING UNIFORM CONTACT PLUGS AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes. | 08-12-2010 |
| 20100243981 | Phase-change random access memory device - A phase-change random access memory device includes an isolation layer structure, an insulating interlayer, a spacer, a switching element and a phase-change material (PCM) layer. The isolation layer structure is in a trench on a substrate, defines an active region in the substrate, and has a recess at an upper portion thereof. The insulating interlayer has an opening partially exposing the active region and the isolation layer structure. The spacer is on a sidewall of the opening and fills the recess. The switching element is in the opening on the exposed active region. The PCM layer is electrically connected to the switching element. | 09-30-2010 |
