| Patent application number | Description | Published |
|---|
| 20080224728 | On-die termination circuit of semiconductor memory apparatus - An on-die termination circuit of a semiconductor memory apparatus includes a comparator that compares a voltage corresponding to a normal code with a reference voltage to output a comparison signal. A code adjusting unit varies the normal code according to the comparison signal, outputs the varied normal code, and resets the normal code to a predetermined reset code or a variable fuse code. | 09-18-2008 |
| 20090052257 | NONVOLATILE SEMICONDUCTOR MEMORIES FOR PREVENTING READ DISTURBANCE AND READING METHODS THEREOF - A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line. | 02-26-2009 |
| 20100054073 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a clock inputting unit configured to receive a system clock and a data clock, a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock and determining a phase of the data division clock according to a division control signal, a phase dividing unit configured to generate a plurality of multiple-phase data division clocks each having a predetermined phase difference according to the data division clock, and a first phase detecting unit configured to detect a phase of the system clock based on a predetermined selection clock among the multiple-phase data division clocks, and generate the division control signal according to the detection result. | 03-04-2010 |
| 20100060329 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a clock input unit configured to receive a system clock and a data clock externally; a phase dividing unit configured to generate a plurality of multi-system clocks in response to the system clock, wherein each of the multi-system clocks has an individual phase difference; a phase detecting unit configured to detect phase differences between the plurality of multi-system clock and the data clock and to generating generate a training information signal in response to the detection result; and a signal transmitting unit configured to transmit the training information signal. | 03-11-2010 |
| 20100165758 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - The semiconductor memory device includes a data input/output unit configured to input data synchronously with a data clock and to output the data to a memory cell in response to an output strobe signal; and an output strobe signal generation unit configured to output the output strobe signal, wherein the output strobe signal is synchronized with a system clock in response to a write command regardless of whether the semiconductor memory device is in a write training mode. | 07-01-2010 |
| 20110050294 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division clocks each of which has the phase difference of a predetermined size by dividing a frequency of the data clock and to determine whether or not phases of the plurality of multi-phase data frequency division clocks are reversed in response to a frequency division control signal, and a first phase detecting block to detect a phase of the system clock based on a phase of a first selected clock that is predetermined among the plurality of multi-phase data frequency division clocks and to is determine a logic level of the frequency division control signal in response to the detected result. | 03-03-2011 |
| 20110050295 | SEMICONDUCTOR DEVICE - A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result. | 03-03-2011 |
| 20110161732 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period. | 06-30-2011 |
