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| 20110072440 | PARALLEL PROCESSING SYSTEM AND METHOD - A parallel processing system determines whether to drive all or some processors so as to process data that are input based on capacity or time for processing the input data. Also, the system temporarily stores the data that are processed and output by the respective processors, and controls the same to be output when it becomes the calculated output time based on the traffic processing time for the input data. | 03-24-2011 |
| 20110113218 | CROSS FLOW PARALLEL PROCESSING METHOD AND SYSTEM - Provided is a cross flow parallel processing method and system that may process multiple data flows and increase a parallel processing rate in a multi-processor that processes multiple cross data flows. | 05-12-2011 |
| 20110145276 | APPARATUS AND METHOD FOR PARALLEL PROCESSING DATA FLOW - Provided is a data flow parallel processing apparatus and method. The data flow parallel processing apparatus may include a flow discriminating unit to discriminate a flow of input first data, a processor allocating unit to allocate, to the first data, a processor that is not operating among a plurality of processors, a sequence determining unit to determine a sequence number of the first data when a second data having the same flow as the discriminated flow is being processed by any one processor composing the plurality of processors, and an alignment unit to receive the first data processed by the allocated processor and to output the received first data based on the determined sequence number. | 06-16-2011 |
| 20110149741 | APPARATUS AND METHOD FOR PROCESSING MULTI-LAYER PACKET - Provided is an apparatus and method for inspecting a multi-layer packet. The apparatus may include a lower layer processing unit to generate lower layer hash information based on a lower layer packet of the multi-layer packet, and to perform a first processing with respect to a flow of the multi-layer packet, in association with the generated lower layer hash information, and a higher layer preprocessing unit to perform a second processing with respect to a flow of the multi-layer packet where the first processing is performed, in association with the lower layer hash information. | 06-23-2011 |
| 20110153710 | APPARATUS AND METHOD FOR PARALLEL-PROCESSING DATA FLOW - Provided is a data flow-parallel processing apparatus and method. The data flow-parallel processing apparatus may include a lower layer processing unit to identify a flow of inputted first data, a distribution unit to select, from among a plurality of upper layer processing units, an upper layer processing unit corresponding to the flow, and to transmit the first data to the selected upper layer processing unit, and an upper layer processing unit to process an upper layer packet of the first data, based on a local memory corresponding to the flow from among a plurality of local memories. | 06-23-2011 |
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| 20110049572 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a 2-Dimensional Electron Gas (2DEG) formed therewithin; a first ohmic electrode disposed on a central region of the semiconductor layer; a second ohmic electrode which is formed on the edge regions of the semiconductor layer in such a manner to be disposed to be spaced apart from the first ohmic electrodes, and have a ring shape surrounding the first ohmic electrode; and a Schottky electrode part which is formed on the central region to cover the first ohmic electrode and is formed to be spaced apart from the second ohmic electrode. | 03-03-2011 |
| 20110057231 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer disposed on the base substrate; first ohmic electrodes disposed on a central region of the first semiconductor layer; a second ohmic electrode having a ring shape surrounding the first ohmic electrodes, on edge regions of the first semiconductor layer; a second semiconductor layer interposed between the first ohmic electrodes and the first semiconductor layer; and a Schottky electrode part which covers the first ohmic electrodes on the central regions, and is spaced apart from the second ohmic electrode. | 03-10-2011 |
| 20110057233 | Semiconductor component and method for manufacturing of the same - The present invention provides a semiconductor component. The semiconductor component in accordance with the present invention includes a lower layer including a low resistance layer and a high resistance layer with higher resistivity than the low resistance layer while surrounding a lateral surface of the low resistance layer; a source electrode disposed on a front surface of the high resistance layer; a gate structure disposed on a front surface of the low resistance layer; a drain structure disposed on a rear surface of the low resistance layer; and a base substrate surrounding the drain structure on a rear surface of the high resistance layer. | 03-10-2011 |
| 20110057234 | Semiconductor device and method for manufacturing of the same - Disclosed is a semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; an ohmic electrode part which has ohmic electrode lines disposed in a first direction, on the semiconductor layer; and a Schottky electrode part which is disposed to be spaced apart from the ohmic electrode lines on the semiconductor layer and includes Schottky electrode lines disposed in the first direction, wherein the Schottky electrode lines and the ohmic electrode lines are alternately disposed in parallel, and the ohmic electrode part further includes first ohmic electrodes covered by the Schottky electrode lines on the semiconductor layer. | 03-10-2011 |
| 20110057257 | Semiconductor device and method for manufacturing the same - The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a recess structure formed thereon; a gate structure covering the recess structure; a source electrode and a drain electrode which are disposed to be spaced apart from each other with respect to the gate structure interposed therebetween, on the semiconductor layer, wherein the semiconductor layer having an upper layer whose thickness is increased toward a first direction facing the drain electrode from the gate structure. | 03-10-2011 |
| 20110057286 | Semiconductor device and method for manufacturing of the same - The present invention provides a semiconductor device including: a base substrate; a first semiconductor layer which is disposed on the base substrate and has a front surface and a rear surface opposite to the front surface; first ohmic electrodes disposed on the front surface of the first semiconductor layer; a second ohmic electrode disposed on the rear surface of the first semiconductor layer; a second semiconductor layer interposed between the first semiconductor layer and the first ohmic electrodes; and a Schottky electrode part which covers the first ohmic electrodes on the front surface of the first semiconductor layer. | 03-10-2011 |
| 20110140121 | ENHANCEMENT NORMALLY OFF NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device. | 06-16-2011 |
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| 20110233520 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device including a base substrate; a semiconductor layer formed on the base substrate and having a mesa protrusion including a receiving groove; a source electrode and a drain electrode disposed to be spaced apart from each other on the semiconductor layer, the source electrode having a source leg and the drain electrode having a drain leg; and a gate electrode insulated from the source electrode and the drain electrode and having a recess part received into the receiving groove. The mesa protrusion has a superlattice structure including at least one trench at an interface between the mesa protrusion and the source electrode and between the mesa protrusion and the drain electrode, respectively, and the source leg and the drain leg are received in the trench. | 09-29-2011 |
| 20110233612 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device having a High Electron Mobility Transistor (HEMT) structure allowing for enhanced performance and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer provided on the base substrate; a source electrode, a gate electrode and a drain electrode provided on the semiconductor layer to be spaced apart from one another; and an ohmic-contact layer partially provided at an interface between the drain electrode and the semiconductor layer. | 09-29-2011 |
| 20110233613 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There are provided a semiconductor device and a method for manufacturing the same. The semiconductor device according to the present invention includes a base substrate; a semiconductor layer that includes a receiving groove and a protrusion part formed on the base substrate, a first carrier injection layer and at least two insulating layers formed to traverse the first carrier injection layer formed in the semiconductor layer, and a second carrier injection layer spaced apart from the first carrier injection layer formed on the protrusion part; a source electrode and a drain electrode that are disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode that is insulated from the source electrode and the drain electrode and has a recess part recessed into the receiving groove, wherein the lowest end portion of the receiving groove contacts the uppermost layer of the first carrier injection layer and the insulating pattern disposed at the innermost side of the semiconductor layer among the insulating patterns traverses the entire layer forming the first carrier injection layer and is disposed at the outer side of both side end portions in the thickness direction of the receiving groove. | 09-29-2011 |
| 20110233623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer having a receiving groove, a protrusion part, a first carrier injection layer, at least two insulating patterns, and a second carrier injection layer provided on the base substrate, the insulating patterns being disposed to traverse the first carrier injection layer and the second carrier injection layer being spaced apart from the first carrier injection layer and disposed on a lower portion of the protrusion part; a source electrode and a drain electrode disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode insulated from the source electrode and the drain electrode and having a recess part recessed into the receiving groove, wherein a lowest portion of the receiving groove contacts an uppermost layer of the first carrier injection layer or is disposed above the uppermost layer thereof, and an insulating pattern, disposed at an innermost portion of the semiconductor layer among the insulating patterns, traverses the first carrier injection layer and is disposed at the outside of both sides of the receiving groove in a thickness direction thereof. | 09-29-2011 |
