Patent application number | Description | Published |
20080205113 | Inter-transmission multi memory chip, system including the same and associated method - A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip. | 08-28-2008 |
20080208537 | CIRCUIT MEASURING OPERATING SPEED AND RELATED SEMICONDUCTOR MEMORY DEVICE - A circuit measuring the operating speed of a semiconductor memory chip in relation to a defined asynchronous access time is disclosed. The circuit includes a test signal path extending between a test input pad and a test output pad and is formed by a plurality of test signal path segments and at least one delay element associated with at least one of the plurality of test signal path segments, such that a delay time for a test signal communicated through the test signal path is indicative of the actual asynchronous access time for the semiconductor memory chip. Each one of the plurality of test signal path segments is either an interior test signal path segment or an exterior test signal path segment. | 08-28-2008 |
20080256414 | SYSTEM AND DEVICE WITH ERROR DETECTION/CORRECTION PROCESS AND METHOD OUTPUTTING DATA - A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane. | 10-16-2008 |
20080273623 | SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFERENTIAL SIGNALING - In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals. | 11-06-2008 |
20080295605 | STRESS DETECTION CIRCUIT AND SEMICONDUCTOR CHIP INCLUDING SAME - A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed. | 12-04-2008 |
20090039492 | STACKED MEMORY DEVICE - A semiconductor memory device includes a stacked plurality of interposer chips, each interposer chip seating a smaller corresponding memory chip, wherein a lowermost interposer chip in the stacked plurality of interposer chips is mounted on a buffer chip. Each one of the stacked plurality of interposer chips includes a central portion having bond pads seating the corresponding memory device and a peripheral portion having a plurality of through silicon vias (TSVs). The respective pluralities of TSVs for adjacent interposer chips in the stacked plurality of interposer chips are connected via vertical connection elements to form multiple internal signal paths communicating write data from and read data to the buffer chip from respective memory chips. | 02-12-2009 |
20090091333 | STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O - The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths. | 04-09-2009 |
20090091962 | MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY - A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips. | 04-09-2009 |
20090125687 | METHOD OF CONTROLLING INTERNAL VOLTAGE AND MULTI-CHIP PACKAGE MEMORY PREPARED USING THE SAME - The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of memory chips coupled to the transfer memory chip, each of the plurality of memory chips including an internal voltage generating circuit, the transfer memory chip configured to receive a plurality of command signals from outside the MCP memory device, the transfer memory chip further configured to output a plurality of control signals to the plurality of memory chips based on the plurality of command signals. Embodiments of the invention also relate to a method of controlling an internal voltage of the MCP memory device. | 05-14-2009 |
20090147559 | MEMORY CELL ARRAY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array. | 06-11-2009 |
20090303802 | SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM HAVING TERMINATION RESISTOR UNITS - A semiconductor memory module includes a memory module board having at least one semiconductor memory device. The semiconductor memory device includes a data input buffer that receives data and a first reference voltage via first and second input terminals, a command/address buffer that receives a command/address signal and a second reference voltage via first and second input terminals, and a first termination resistor unit connected to the first input terminal of the data input buffer. The semiconductor memory module further includes a second termination resistor unit located on the memory module board and connected to an internal command/address bus. The first termination resistor unit includes a first resistor connected between a first voltage source and the first input terminal of the data input buffer, and the second termination resistor unit includes a second resistor connected between a second voltage source and the first input terminal of the command/address input buffer. | 12-10-2009 |
20100018760 | Semiconductor device and semiconductor package including the same - A semiconductor device includes a first substrate including at least one first well region and first impurity regions on portions of the substrate and a bias voltage plate on a surface of the substrate. A semiconductor device may be of a three dimensional stack structure, and in example embodiments, the semiconductor device may further include a through contact plug substantially perpendicularly penetrating at least one substrate and at least one bias voltage plate. Therefore, a design margin of a semiconductor device may be enhanced and a bias voltage may be provided reliably. | 01-28-2010 |
20100124138 | Semiconductor memory device having variable-mode refresh operation - A semiconductor memory device includes a bit line sense amplifier, a bit line pair that includes a bit line and a complementary bit line, the bit line and the complementary bit line of the bit line pair each being coupled to the bit line sense amplifier, a memory cell array having a plurality of memory banks, the memory banks including word lines and a plurality of memory cells, and a word line activation control unit that performs a control to access data corresponding to an externally same address in at least two memory cells by simultaneously activating a predetermined number of word lines from among the word lines sharing the bit line sense amplifier, and the word line activation control unit operates in response to a determination mode allowing signal that is set in accordance with a used memory density. | 05-20-2010 |
20100157709 | Semiconductor memory device having shared temperature control circuit - A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding memory bank. The shared control circuit is connected to the plurality of temperature sensing circuits and a plurality of refresh circuits for refreshing the plurality of memory banks, performs calibration on the plurality of temperature sensing circuits, performs digital processing on signals for separately controlling refresh intervals for the plurality of memory banks, and transmits the processed signals to the plurality of refresh circuits. Therefore, the refresh intervals for individual channels or banks are separately or selectively controlled. Further, since the plurality of temperature sensing circuits are connected to the shared temperature control circuit, the occupied area of the circuits in a chip is reduced or minimized. | 06-24-2010 |
20100177576 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifier driving signal. The sense amplifier driving signal driver includes a first driving signal driver configured to drive via a transmission line the sense amplifier driving signal in response to a first sense amplifier control signal, and a second driving signal driver configured to drive via the transmission line the sense amplifier driving signal in response to a second sense amplifier control signal. The controller activates the first sense amplifier control signal in response to an active command, and toggles the second sense amplifier control signal while the first sense amplifier control signal is activated. | 07-15-2010 |
20100191880 | MEMORY MODULE CAPABLE OF IMPROVING THE INTEGRITY OF SIGNALS TRANSMITTED THROUGH A DATA BUS AND A COMMAND/ADDRESS BUS, AND A MEMORY SYSTEM INCLUDING THE SAME - A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type. | 07-29-2010 |
20100226185 | SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM HAVING TERMINATION RESISTOR UNITS - A semiconductor memory module includes a memory module board having at least one semiconductor memory device, an advanced memory buffer (AMB) for receiving the data and the command/address signal from a host and providing the data and the command/address signal to the at least one semiconductor memory device, and a second termination resistor unit located on the memory module board and electrically connected to the AMB. The at least one semiconductor memory device includes a data input buffer for receiving data via a first input terminal and receiving a first reference voltage via a second input terminal, a command/address input buffer for receiving a command/address signal via a first input terminal and receiving a second reference voltage via a second input terminal, and a first termination resistor unit connected to the first input terminal of the data input buffer. | 09-09-2010 |
20100226188 | FIRST DELAY LOCKING METHOD, DELAY-LOCKED LOOP, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal. | 09-09-2010 |
20100309742 | METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY - Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports. | 12-09-2010 |
20100322021 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal. | 12-23-2010 |
20110044084 | MULTI-CHIP MEMORY DEVICE WITH STACKED MEMORY CHIPS, METHOD OF STACKING MEMORY CHIPS, AND METHOD OF CONTROLLING OPERATION OF MULTI-CHIP PACKAGE MEMORY - A multi-chip memory device includes a transfer memory chip communicating input/output signals, a stacked plurality of memory chips each including a memory array having a designated bank, and a signal path extending upward from the transfer memory chip through the stack of memory chips to communicate input/output signals, wherein each bank of each memory chip in the stacked plurality of memory chips is commonly addressed to provide read data during a read operation and receive write data during a write operation, and vertically aligned within the stacked plurality of memory chips. | 02-24-2011 |
20110069572 | ROW ADDRESS CODE SELECTION BASED ON LOCATIONS OF SUBSTANDARD MEMORY CELLS - A memory device identifies memory blocks that contain substandard memory cells. The memory device then determines row address codes to apply to the memory blocks during refresh operations. The row address codes determine which memory blocks of the memory block are refreshed together. The row address codes are designed to ensure that memory blocks having substandard memory cells, which must be refreshed more frequently than other cells, are refreshed together, while memory blocks without substandard memory cells are refreshed together. | 03-24-2011 |
20110072205 | MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell. | 03-24-2011 |
20110093235 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip. | 04-21-2011 |
20110095814 | CIRCUIT AND METHOD FOR GENERATING INTERNAL VOLTAGE, AND SEMICONDUCTOR DEVICE HAVING THE CIRCUIT - An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal. | 04-28-2011 |
20110116335 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM INCLUDING THE SAME - A semiconductor memory device includes a cell array unit having a plurality of banks each having a plurality of blocks, and a refresh controller configured to set at least one of the blocks as a test block, perform a refresh operation on the blocks except for the test block in a self-refresh operation period, determine a refresh period of the test block, and then set another one of the blocks as the test block. | 05-19-2011 |
20110199808 | MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED - A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block. | 08-18-2011 |
20110199836 | BIT-LINE SENSE AMPLIFIER, SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME, AND METHOD OF TESTING BIT-LINE MICRO-BRIDGE DEFECT - The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line. | 08-18-2011 |
20110248740 | STACKED SEMICONDUCTOR APPARATUS WITH CONFIGURABLE VERTICAL I/O - The present invention provides an apparatus including a stacked plurality of devices and a related method. The apparatus includes a stacked plurality of devices including a master device and at least one secondary device; a plurality of segments, each segment being associated with one of the stacked plurality of devices; and a plurality of N vertical connection paths traversing the stacked plurality of devices. The apparatus further includes a plurality of M vertical signal paths configured from the plurality of N vertical connections paths, wherein M is less than N, and at least one of the plurality of M vertical signal paths is a merged vertical signal path adaptively configured by the master device using at least one segment from each one of at least two of the plurality of N vertical connection paths. | 10-13-2011 |
20110314349 | DATA TRANSMITTING AND RECEIVING SYSTEM - A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed. | 12-22-2011 |
20120039404 | SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFERENTIAL SIGNALING - In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals. | 02-16-2012 |
20120188834 | SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal. | 07-26-2012 |
20130142000 | METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY - Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports. | 06-06-2013 |
20130163692 | SYSTEM AND METHOD FOR SELECTIVELY PERFORMING SINGLE-ENDED AND DIFFERENTIAL SIGNALING - In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals. | 06-27-2013 |
20130272047 | MEMORY DEVICE FROM WHICH DUMMY EDGE MEMORY BLOCK IS REMOVED - A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block. | 10-17-2013 |