Patent application number | Description | Published |
20080281896 | INDUSTRIAL CONTROLLER - A first arithmetic operator ( | 11-13-2008 |
20080320331 | CONTROL APPARATUS - For a control apparatus to be boundary scan testable even when running, including processor cores in an operator to be capable of self-repairing a troubling part, an operator ( | 12-25-2008 |
20090287867 | BUS SIGNAL CONTROL CIRCUIT AND SIGNAL PROCESSING CIRCUIT HAVING BUS SIGNAL CONTROL CIRCUIT - A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present. | 11-19-2009 |
20100251055 | PCI.EXPRESS COMMUNICATION SYSTEM AND COMMUNICATION METHOD THEREOF - When a transaction layer circuit detects an error, error information in respect of transmission data is set in a TLP digest. The method includes: a step in which, at an endpoint ( | 09-30-2010 |
20120030402 | PCI EXPRESS TLP PROCESSING CIRCUIT AND RELAY DEVICE PROVIDED WITH THIS - A PCI Express TLP processing circuit ( | 02-02-2012 |
20120096467 | MICROPROCESSOR OPERATION MONITORING SYSTEM - A microprocessor operation monitoring system whose own tasks are constituted by associating beforehand the task number of the task that is next to be started up, for each of the tasks constituting the program, and abnormality of microprocessor operation is detected by comparing and determining whether or not the announced task and the task to be started up match. | 04-19-2012 |
20120143535 | SUBSTATION INSTRUMENT CONTROL SYSTEM - A substation instrument control system is disclosed. The substation instrument control system includes a plurality of transformers that generate a plurality of waveform signals representing electric properties of a substation instrument main body. A merging unit is communicatively coupled to the plurality of transformers and includes a signal processing unit and a control unit. The signal processing unit receives the plurality of waveform signals from the plurality of transformers and converts the plurality of waveform signals to a digital signal. The control unit controls operation of the signal processing unit using a setting data. An intelligent electronic device is communicatively coupled to the merging unit and receives the digital signal from the merging unit. | 06-07-2012 |
20120185858 | PROCESSOR OPERATION MONITORING SYSTEM AND MONITORING METHOD THEREOF - A processor includes a computation unit; a storage unit storing a program; and a data transmission circuit that transmits to an operation monitoring unit a signal corresponding to an instruction for reporting the execution stage of the program. The operation monitoring unit: includes a transition operation identification. circuit and a loop processing identification circuit. The transition operation identification circuit receives a start ID instruction with an attached ID that identifies a task; a termination ID instruction that identifies termination of task operation; and if the task is execution of loop processing, a loop instruction that reports the maximum value of the number of times of this loop processing. The transition operation identification circuit identifies success of the transition operations of the tasks of the program, based on the ID instructions. The loop processing identification circuit identifies abnormality of the number of times of loop processing. | 07-19-2012 |
20130082739 | CLOCK DIAGNOSIS CIRCUIT - A clock diagnosis circuit includes: a delay circuit to delay the clock by a prescribed time which is not more than the clock pulse width; an integral multiplication delay circuit to delay a delayed clock outputted from the delay circuit by a prescribed number of cycles; a first exclusive OR circuit to encode the clock using the delayed clock; a second exclusive OR circuit to decode an output of the first exclusive OR circuit using an output of the integral multiplication delay circuit; and a comparison circuit to compare the clock with an output of the second exclusive OR circuit to thereby detect a malfunction of the clock. | 04-04-2013 |