Patent application number | Description | Published |
20130322763 | APPARATUS AND METHOD FOR TRACKING OBJECT USING FEATURE DESCRIPTOR, AND APPARATUS AND METHOD FOR REMOVING GARBAGE FEATURE - An apparatus and method for tracking an object using a feature descriptor and an apparatus and method for removing a garbage feature are disclosed. A feature descriptor generation unit generates a plurality of features descriptors indicating information of a plurality of features extracted from an input image from which an object of interest is desired to be detected. A matching unit matches the feature descriptors with feature descriptors of a target object stored in advance, and determines the feature descriptors of the object of interest corresponding to the target object. A feature point removal unit removes feature descriptors that do not meet a geometric comparison condition from among the feature descriptors of the object of interest, and establishes final feature descriptors of the object of interest. | 12-05-2013 |
20140355823 | VIDEO SEARCH APPARATUS AND METHOD - The present invention relates to a video search apparatus and method, and more particularly, to a video search apparatus and method which can be used to search video data collected by a video capture apparatus, such as a closed circuit television (CCTV), for information desired by a user. | 12-04-2014 |
20140355829 | PEOPLE DETECTION APPARATUS AND METHOD AND PEOPLE COUNTING APPARATUS AND METHOD - According to an aspect of the present invention, there is provided a people counting apparatus including: a reception unit which receives a video of an area including an entrance captured by a video capture device; a line setting unit which sets an inline at the entrance and sets an outline such that a specific region is formed on a side of the inline; a detection unit which detects moving objects in the video using information differences between frames of the received video and detects human moving objects among the detected moving objects; a tracking unit which tracks the movement of each of the detected moving objects; and a counting unit which determines whether each of the moving objects passed the inline and the outline based on the tracked movement of each of the moving objects and counts the number of people based on the determination result. | 12-04-2014 |
Patent application number | Description | Published |
20080237613 | Ac Light Emitting Device Having Photonic Crystal Structure and Method of Fabricating the Same - Disclosed is an AC light emitting device having photonic crystal structures and a method of fabricating the same. The light emitting device includes a plurality of light emitting cells and metallic wirings electrically connecting the light emitting cells with one another. Further, each of the light emitting cells includes a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on one region of the first conductive type semiconductor layer, and an active layer interposed between the first and second conductive type semiconductor layers. In addition, a photonic crystal structure is formed in the second conductive type semiconductor layer. The photonic crystal structure prevents light emitted from the active layer from laterally propagating by means of a periodic array, such that light extraction efficiency of the light emitting device can be improved. Furthermore, the metallic wirings electrically connect a plurality of light emitting cells with one another such that an AC light emitting device can be provided. | 10-02-2008 |
20090170847 | Imidazopyridine Derivatives Inhibiting Protein Kinase Activity, Method for the Preparation Thereof and Pharmaceutical Composition Containing Same - The inventive imidazopyridine derivative can be used in a pharmaceutical composition for preventing or treating diseases such as diabetes, obesity, dementia, cancer, and inflammation, since it can efficiently inhibit the activities of several protein kinases including glycogen synthase kinase-3 (GSK-3), aurora kinase, extracellular signal-regulated kinase (ERK), protein kinase B (AKT), and the likes, to control signal transductions thereof. | 07-02-2009 |
20090311816 | AC LIGHT EMITTING DEVICE HAVING PHOTONIC CRYSTAL STRUCTURE AND METHOD OF FABRICATING THE SAME - Disclosed is an AC light emitting device having photonic crystal structures and a method of fabricating the same. The light emitting device includes a plurality of light emitting cells and metallic wirings electrically connecting the light emitting cells with one another. Further, each of the light emitting cells includes a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on one region of the first conductive type semiconductor layer, and an active layer interposed between the first and second conductive type semiconductor layers. In addition, a photonic crystal structure is formed in the second conductive type semiconductor layer. The photonic crystal structure prevents light emitted from the active layer from laterally propagating by means of a periodic array, such that light extraction efficiency of the light emitting device can be improved. Furthermore, the metallic wirings electrically connect a plurality of light emitting cells with one another such that an AC light emitting device can be provided. | 12-17-2009 |
20110157523 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device includes: upper and lower substrates facing and spaced apart from each other; a liquid crystal layer between the upper and lower substrates; an upper polarizing plate on an outer surface of the upper substrate; and a lower polarizing plate on an outer surface of the lower substrate, wherein one of the upper and lower polarizing plates includes a first polarizing layer having a first optical axis and a first absorption axis perpendicular to each other, and an other of the upper and lower polarizing plates includes a second polarizing layer having a second optical axis and a second absorption axis parallel to each other. | 06-30-2011 |
20130128671 | FLASH MEMORY DEVICE AND PROGRAM METHOD - Disclosed is a flash memory device and programming method that includes; receiving buffer data and determining between a high-speed mode and a reliability mode for buffer data, and upon determining the reliability mode storing the buffer data in a first buffer region, and upon determining the high-speed mode storing the buffer data in a second buffer region. The memory cell array of the flash memory including a main region and a separately designated buffer region divided into the first buffer region and second buffer region. | 05-23-2013 |
20140099870 | GRINDING APPARATUS FOR A SUBSTRATE - A substrate grinding apparatus according to an exemplary embodiment of the present invention includes a grinding wheel grinding an object substrate, a nozzle unit spraying cooling water to the object substrate and the grinding wheel in a plurality of directions, and a cooling water controller connected to the nozzle unit and controlling spray speed and pressure of the cooling water, in which the nozzle unit includes a cleansing nozzle cleansing the grinding wheel, a cooling nozzle cooling the grinding wheel, and a surface protecting nozzle cooling the object substrate. | 04-10-2014 |
20140369942 | COMPOSITION COMPRISING TAUROURSODEOXYCHOLIC ACID - Provided is a method for preventing or treating a periodontal disease; or a method for improving oral hygiene, including administering a pharmaceutical composition containing tauroursodeoxycholic acid as an active ingredient. | 12-18-2014 |
20150336944 | Sodium Channel Blockers, Preparation Method Thereof and Use Thereof - The present invention relates to a compound having a blocking effect against sodium ion channels, particularly Nav1.7, a preparation method thereof and the use thereof. A compound represented by formula 1 according to the invention, or a pharmaceutically acceptable salt, hydrate, solvate or isomer thereof may be effectively used for the prevention or treatment of pain, for example, acute pain, chronic pain, neuropathic pain, post-surgery pain, migraine, arthralgia, neuropathy, nerve injury, diabetic neuropathy, neuropathic disease, epilepsy, arrhythmia, myotonia, ataxia, multiple sclerosis, irritable bowel syndrome, urinary incontinence, visceral pain, depression, erythromelalgia, or paroxysmal extreme pain disorder (PEPD). | 11-26-2015 |
Patent application number | Description | Published |
20140043920 | MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data. | 02-13-2014 |
20140219044 | MEMORY MODULE AND MEMORY SYSTEM COMPRISING SAME - A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal. | 08-07-2014 |
20150340074 | MEMORY MODULE HAVING ADDRESS MIRRORING FUNCTION - A memory module having an address minoring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored. | 11-26-2015 |
Patent application number | Description | Published |
20140040541 | METHOD OF MANAGING DYNAMIC MEMORY REALLOCATION AND DEVICE PERFORMING THE METHOD - A method of managing dynamic memory reallocation includes receiving an input address including a block bit part, a tag part, and an index part and communicating the index part to a tag memory array, receiving a tag group communicated by the tag memory array based on the index part, analyzing the tag group based on the block bit part and the tag part and changing the block bit part and the tag part based on a result of the analysis, and outputting an output address including a changed block bit part, a changed tag part, and the index part. | 02-06-2014 |
20140149652 | MEMORY SYSTEM AND METHOD OF MAPPING ADDRESS USING THE SAME - In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module. | 05-29-2014 |
20140208071 | ADAPTIVE SERVICE CONTROLLER, SYSTEM ON CHIP AND METHOD OF CONTROLLING THE SAME - A system on chip (SOC) includes a slave device, a plurality of master devices, an interconnect device and a plurality of service controllers. The master devices generate requests to demand services from the slave device. The interconnect device is coupled to the slave device and the master devices through respective channels, and the interconnect device performs an arbitrating operation on the requests. The service controllers control request flows from the master devices adaptively depending on an operational environment change of the SOC. | 07-24-2014 |
20150049570 | MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, OPERATING METHOD THEREOF - In one embodiment, the memory device includes at least one memory bank including first and second subbanks, and control logic configured to control storing data into the memory bank. The control logic is configured to activate the first subbank and to precharge the second subbank in response to a first activate command for the first subbank. | 02-19-2015 |
20150081989 | SEMICONDUCTOR DEVICES INCLUDING APPLICATION PROCESSOR CONNECTED TO HIGH-BANDWIDTH MEMORY AND LOW-BANDWIDTH MEMORY, AND CHANNEL INTERLEAVING METHOD THEREOF - A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device. | 03-19-2015 |
20150155055 | TEST METHOD OF SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area. | 06-04-2015 |
20150227481 | SYSTEM INTERCONNECT AND OPERATING METHOD OF SYSTEM INTERCONNECT - A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals. | 08-13-2015 |
Patent application number | Description | Published |
20080230832 | TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck. | 09-25-2008 |
20100096690 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA - A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region. | 04-22-2010 |
20100105183 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL AREA AND FABRICATION METHOD THEREOF - A semiconductor device includes an active region defining at least four surfaces, the four surfaces including first, second, third, and fourth surfaces, a gate insulation layer formed around the four surfaces of the active region, and a gate electrode formed around the gate insulation layer and the four surfaces of the active region. | 04-29-2010 |
Patent application number | Description | Published |
20080230769 | Electronic device, field effect transistor including the electronic device, and method of manufacturing the electronic device and the field effect transistor - Provided is an electronic device, a field effect transistor having the electronic device, and a method of manufacturing the electronic device and the field effect transistor. The electronic device includes: a substrate; a first electrode and a second electrode which are formed in parallel to each other on the substrate, each of the first electrode and the second electrode comprising two electrode pads separated from each other and a heating element that connect the two electrode pads; a catalyst metal layer formed on the heating element of the first electrode; and a carbon nanotube connected to the second electrode by horizontally growing from the catalyst metal layer; wherein the heating elements are separated from the substrate by etching the substrate under the heating elements of the first and the second electrodes. | 09-25-2008 |
20090186148 | Method of fabricating organic light emitting device - In a method of forming a pattern of an organic light emitting device (OLED), an organic material is evaporated in a predetermined pattern by using a pre-patterned heating element, and the evaporated organic material is transferred to a substrate where the OLED is formed. The method includes preparing a template having a heating element in a pattern corresponding to a multilayered structure of an OLED including a plurality of functional layers; forming an organic layer on the heating element; drawing a substrate for the OLED near to the heating element of the template; and transferring the organic layer on the heating element to the substrate by evaporating the organic layer using the heating element. | 07-23-2009 |
20110124184 | Method of forming polysilicon, thin film transistor using the polysilicon, and method of fabricating the thin film transistor - A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s). | 05-26-2011 |
20130126880 | Method Of Forming Polysilicon, Thin Film Transistor Using The Polysilicon, And Method Of Fabricating The Thin Film Transistor - A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s). | 05-23-2013 |
Patent application number | Description | Published |
20120056237 | SEMICONDUCTOR COMPOUND STRUCTURE AND METHOD OF FABRICATING THE SAME USING GRAPHENE OR CARBON NANOTUBES, AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR COMPOUND STRUCTURE - A semiconductor compound structure and a method of fabricating the semiconductor compound structure using graphene or carbon nanotubes, and a semiconductor device including the semiconductor compound structure. The semiconductor compound structure includes a substrate; a buffer layer disposed on the substrate, and formed of a material including carbons having hexagonal crystal structures; and a semiconductor compound layer grown and formed on the buffer layer. | 03-08-2012 |
20120127562 | ACTIVE OPTICAL DEVICE USING PHASE CHANGE MATERIAL - An active optical device is provided. The active optical device includes an optically variable layer having a refractive index which changes according to temperature; and a temperature control unit that controls a temperature of one or more regions of the optically variable layer. | 05-24-2012 |
20120132643 | MICROHEATER AND MICROHEATER ARRAY - A microheater and a microheater array are provided. The microheater includes a substrate, a column disposed on the substrate and a bridge supported by the column. A width of a portion of a bridge formed on the column is less than a width of a portion of the bridge that does not contact the column. The bridge may include a spring component. | 05-31-2012 |
20120154715 | ACTIVE OPTICAL DEVICE EMPLOYING REFRACTIVE INDEX VARIABLE REGIONS - An active optical device includes a substrate; a plurality of refractive index variable regions formed on the substrate; and a voltage applier which applies an electric field to the plurality of refractive index variable regions. | 06-21-2012 |
20120222732 | STACKED STRUCTURE INCLUDING VERTICALLY GROWN SEMICONDUCTOR, P-N JUNCTION DEVICE INCLUDING THE STACKED STRUCTURE, AND METHOD OF MANUFACTURING THEREOF - A stacked structure may include semiconductors or semiconductor layers grown on an amorphous substrate. A light-emitting device and a solar cell may include the stacked structure including the semiconductors grown on the amorphous substrate. A method of manufacturing the stacked structure, and the light-emitting device and the solar cell including the stacked structure may involve growing a crystalline semiconductor layer on an amorphous substrate. | 09-06-2012 |
20130135709 | ACTIVE OPTICAL DEVICE AND DISPLAY APPARATUS INCLUDING THE SAME - An active optical device and a display apparatus including the same are provided. The active optical device includes: first to third electrodes that are sequentially disposed spaced apart from one another; a first refractive index change layer disposed between the first electrode and the second electrode and in which a refractive index is changed by an electric field; and a second refractive index change layer disposed between the second electrode and the third electrode and in which a refractive index is changed by an electric field. | 05-30-2013 |
20140054599 | FLEXIBLE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A flexible semiconductor device and a method of manufacturing the flexible semiconductor device are provided. The flexible semiconductor device may include at least one vertical semiconductor element that is at least partly embedded in a flexible material layer. The flexible semiconductor device may further include a first electrode formed on a first surface of the flexible material layer and a second electrode formed on a second surface of the flexible material layer. A method of manufacturing a flexible semiconductor device may include separating a flexible material layer, in which the at least one vertical semiconductor element is embedded, from a substrate by weakening or degrading an adhesive force between an underlayer and a buffer layer by using a difference in coefficients of thermal expansion of the underlayer and the buffer layer. | 02-27-2014 |
20140162406 | FLEXIBLE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method of transferring semiconductor elements formed on a non-flexible substrate to a flexible substrate. Also, provided is a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements. A semiconductor element grown or formed on the substrate may be efficiently transferred to the resin layer while maintaining an arrangement of the semiconductor elements. Furthermore, the resin layer acts as a flexible substrate supporting the vertical semiconductor elements. | 06-12-2014 |
20140242782 | METHODS OF TRANSFERRING SEMICONDUCTOR ELEMENTS AND MANUFACTURING SEMICONDUCTOR DEVICES - The present disclosure relates to a method of transferring semiconductor elements from a non-flexible substrate to a flexible substrate. The present disclosure also relates to a method of manufacturing a flexible semiconductor device based on the method of transferring semiconductor elements. The semiconductor elements grown or formed on a non-flexible substrate may be effectively transferred to a resin layer while maintaining an arrangement of the semiconductor elements. The resin layer may function as a flexible substrate for supporting the vertical semiconductor elements. | 08-28-2014 |
20150014630 | TUNNELING DEVICES AND METHODS OF MANUFACTURING THE SAME - A tunneling device may include a tunnel barrier layer, a first material layer including a first conductivity type two-dimensional material on a first surface of the tunnel barrier layer and a second material layer including a second conductivity type two-dimensional material on a second surface of the tunnel barrier layer. The tunneling device may use a tunneling current through the tunnel barrier layer between the first material layer and the second material layer. | 01-15-2015 |
20150060874 | FLEXIBLE ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME - A flexible electric device includes a first electrode on a flexible member, at least one semiconductor element on the first electrode, at least one filling region adjacent to the semiconductor element and a second electrode on the semiconductor element. | 03-05-2015 |
Patent application number | Description | Published |
20100099463 | MOBILE TERMINAL HAVING TOUCH SENSOR-EQUIPPED INPUT DEVICE AND CONTROL METHOD THEREOF - A mobile terminal having a touch sensor-equipped input device and its control method are disclosed. The mobile terminal includes: a user input unit in which a keypad-printed layer and a touch sensor overlap with each other; and a controller that controls an operation mode of the user input unit in a touch pad and/or a touch keypad mode according to whether or not a cursor is in use. | 04-22-2010 |
20100100842 | MOBILE TERMINAL AND CONTROL METHOD THEREOF - Disclosed are a mobile terminal capable of executing web browsing with consideration of a user's convenience, and a control method thereof. The mobile terminal comprises: a wireless communication unit which accesses any web page; a display module for displaying the accessed web page; and a controller for automatically displaying popup windows in a virtual space when the accessed web page has any popup windows. Popup windows can be hidden at the time of web browsing, and the hidden popup windows can be displayed according to a user's necessity. This enhances the user's convenience. | 04-22-2010 |
20150103599 | METHOD OF OPERATING MEMORY DEVICE ASSURING RELIABILITY AND MEMORY SYSTEM - A method of operating a memory device to guarantee program reliability and a memory system using the same are provided. The method includes backing up data stored in the memory cells connected to a first word line, performing a dummy program operation on memory cells connected to a second word line adjacent to the first word line, and performing a recharge program operation on the memory cells connected to the first word line. | 04-16-2015 |
20160015198 | CAN TYPE CONTAINER CHANGEABLE TO TYPE OF CUP OR GLASS - A can type container, changeable to a type of cup or glass, is described and includes: a containing body having a first fastening portion formed on the upper end periphery thereof and a shape of a cone having an outer diameter gradually increased toward the lower end portion thereof; a sealing member adapted to close the lower end periphery of the containing body; a lower cap fastened to the lower end periphery of the containing body in the state where the lower end periphery of the containing body is sealed by the sealing member and having a support member inserted thereinto; and the support member having a corresponding fastening portion to the first fastening portion of the containing body formed at the center thereof in such a manner as to be coupled to the first fastening portion and a base adapted to serve as a support stand. | 01-21-2016 |
Patent application number | Description | Published |
20080197911 | CIRCUIT WITH FUSE/ANTI-FUSE TRANSISTOR WITH SELECTIVELY DAMAGED GATE INSULATING LAYER - A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication. | 08-21-2008 |
20080272430 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench. | 11-06-2008 |
20090010086 | SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential output voltages to a sense amplifier output line pair. The voltage sense amplifier is coupled to the sense amplifier output line pair to amplify the differential output voltages on the sense amplifier output line pair. The voltage sense amplifier is activated at the time later than a time of activation of the current sense amplifier. The output stabilizing circuit is coupled to the sense amplifier output line pair to stabilize the differential output voltages on the sense amplifier output line pair. The output stabilizing circuit has a positive input resistance. Accordingly, the sense amplifier circuit reduces power consumption and an occupied area on a semiconductor chip. | 01-08-2009 |
20100093141 | METHOD OF MANUFACTURING A TRANSISTOR AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening. | 04-15-2010 |
20100127325 | Recessed channel transistors, and semiconductor devices including a recessed channel transistor - A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities. | 05-27-2010 |
20130256770 | TRANSISTOR, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE INCLUDING THE SAME - A semiconductor device including a buried cell array transistor and an electronic device including the same are provided. The device includes a field region in a substrate and the filed region defines an active region. A first source/drain region and a second source/drain region are in the active region. A gate trench is between the first and second source/drain regions, and in the active region and the field region. A gate structure is within the gate trench. The gate structure includes a gate electrode, an insulating gate capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an insulating metal-containing material layer between the insulating gate capping pattern and the active region. | 10-03-2013 |
20130270672 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes first and second storage electrodes formed to be spaced apart from each other on a substrate, an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes, a storage dielectric layer formed to cover the first and second storage electrodes and the continuous support pattern, and a plate electrode formed on the storage dielectric layer. The continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other. | 10-17-2013 |
20150021684 | SEMICONDUCTOR DEVICE HAVING BURIED CHANNEL ARRAY AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of fabricating a semiconductor device, the device including an active region on a substrate, the active region being defined by a field region; gate trenches in the active region of the substrate; gate structures respectively formed in the gate trenches; and at least one carrier barrier layer in the substrate and under the gate trenches. | 01-22-2015 |
20150123238 | SEMICONDUCTOR DEVICES - There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon. | 05-07-2015 |
20150235852 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate. | 08-20-2015 |
Patent application number | Description | Published |
20140123171 | BROADCASTING SIGNAL RECEIVING APPARATUS AND CONTROL METHOD THEREOF - A broadcasting signal receiving apparatus and a control method thereof, the broadcasting signal receiving apparatus including: a signal receiver which receives a broadcasting signal; a signal processor which processes the received broadcasting signal; an interface to which a conditional access module (CAM) that descrambles a scrambled broadcasting signal is connected; and a controller which, if the connection of the CAM through the interface is detected, monitors the broadcasting signal transmitted by the CAM, and if a noise occurs from the broadcasting signal transmitted by the CAM, controls the signal processor to adjust a timing of at least one of a clock signal and a data signal included in the broadcasting signal. Thus, the noise due to the CAM may automatically be compensated and prevent performance of unnecessary compensation process. | 05-01-2014 |
20140313418 | DISPLAY APPARATUS AND CHANNEL SEARCHING METHOD THEREOF - A display apparatus and a method of searching for a channel in the display apparatus includes a plurality of tuners and a plurality of antenna ports respectively connected to the plurality of tuners. The method includes receiving a channel search command; if the channel search command is input, searching for one of the plurality of antenna ports that is connected to a satellite antenna to receive a broadcasting signal, if one of the plurality of antenna ports is connected to the satellite antenna to receive the broadcasting signal, setting one of the plurality of tuners connected to the one antenna port, to a main tuner, and performing a channel search through the tuner set to the main tuner. Therefore, although an antenna port connected to one of the plurality of tuners initially set to a sub tuner, the display apparatus performs a channel search through the corresponding tuner. | 10-23-2014 |