| Patent application number | Description | Published |
|---|
| 20100097870 | SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING OPERATION OF DELAY-LOCKED LOOP CIRCUIT - A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks. | 04-22-2010 |
| 20100102860 | WIDEBAND DELAY-LOCKED LOOP (DLL) CIRCUIT - A wideband delay-locked loop (DLL) circuit includes an internal clock signal generating unit providing an internal control signal by selecting and interpolating between two clock delay signals during a primary phase locking operation. The internal clock signal may be modified by a secondary phase locking operation if more delay is required to phase lock the internal clock signal to an external clock signal. A phase detection/control circuit generates various control signals based on a phase comparison of the internal clock signal and the external clock signal. | 04-29-2010 |
| 20100226188 | FIRST DELAY LOCKING METHOD, DELAY-LOCKED LOOP, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal. | 09-09-2010 |
| 20100259294 | ON-DIE TERMINATION LATENCY CLOCK CONTROL CIRCUIT AND METHOD OF CONTROLLING THE ON-DIE TERMINATION LATENCY CLOCK - A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period. | 10-14-2010 |
| 20100321076 | DELAY-LOCKED LOOP FOR CORRECTING DUTY RATIO OF INPUT CLOCK SIGNAL AND OUTPUT CLOCK SIGNAL AND ELECTRONIC DEVICE INCLUDING THE SAME - A delay-locked loop includes a delay line and a duty correction block. The delay line includes receives an input clock signal and includes a cascade of delay cells for respectively generating a plurality of delayed input clock signals based on the input clock signal. The duty correction block is for correcting a duty ratio of the input clock signal based on a duty ratio of at least one clock signal from among the input clock signal and the plurality of delayed input clock signals in a first duty correction operation in which the duty ratio of the input clock signal is corrected, and correcting a duty ratio of an output clock signal based on the duty ratio of the output clock in a second duty correction operation in which the duty ratio of the output clock signal is corrected. | 12-23-2010 |
| 20110025373 | Semiconductor devices having ZQ calibration circuits and calibration methods thereof - Provided is a semiconductor device for performing a calibration operation without an external ZQ calibration command and a calibration method thereof. The semiconductor device includes a calibration circuit for performing a pull-down calibration operation in response to a pull-down calibration enable signal and a command control unit for generating the pull-down calibration enable signal in response to a DLL reset signal. The calibration method includes adjusting an impedance of a first pull-up resistance structure in response to pull-up calibration codes having a default value. A pull-down calibration enable signal may be generated in response to a DLL reset signal. A voltage of the first node and a reference voltage are compared by a comparator. The comparator outputs pull-down calibration codes based on the comparison. An impedance of a pull-down resistance structure is adjusted, so a resistance of the pull-down resistance structure is equal to a resistance of the first pull-up resistance structure. | 02-03-2011 |
| 20110095795 | SEMICONDUCTOR MEMORY DEVICE HAVING DELAY LOCK LOOP WITH WIDE FREQUENCY RANGE AND DELAY CELL CURRENT REDUCTION SCHEME - A semiconductor memory device includes a delay lock loop (DLL) performing a locking operation at a wide frequency range and reducing current consumption. The semiconductor memory device includes a (DLL) having serially connected delay cells that receive and delay an external clock signal, wherein a predetermined number of delay cells of the serially connected delay cells that are to perform a delay operation are turned on in response to a threshold frequency recognition signal and first and second delay cell on signals, and for generating an internal clock signal; and a controller for generating the threshold frequency recognition signal and the first and second delay cell on signals, which reduce current consumption of each of the serially connected delay cells and increase a period of delay time thereof, if more delay cells are to be turned on when a delay cell indicating a threshold frequency is turned on. | 04-28-2011 |
| 20110109357 | DELAY LOCKED LOOP CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE DELAY LOCKED LOOP CIRCUIT - A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a delay circuit and a phase adjusting circuit. The phase adjusting circuit is configured to receive a clock signal output from the delay circuit, pass the clock signal through a N-divider and a replica path to create a N-divided delay signal, and detect phase information about an external clock signal in response to a rising edge and a falling edge of the N-divided delay signal, wherein N denotes a natural number. The delay circuit is configured to output the clock signal by adjusting a phase of the external clock signal in response to a result of the detection. A semiconductor device, semiconductor system, and method are also disclosed. | 05-12-2011 |
