| Patent application number | Description | Published |
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| 20090150597 | DATA WRITING METHOD FOR FLASH MEMORY AND CONTROLLER USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block. | 06-11-2009 |
| 20090198875 | DATA WRITING METHOD FOR FLASH MEMORY, AND CONTROLLER AND SYSTEM USING THE SAME - A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented. | 08-06-2009 |
| 20100042774 | BLOCK MANAGEMENT METHOD FOR FLASH MEMORY, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME - A block management method for a flash memory chip having multiple planes is provided, wherein each plane has a plurality of physical blocks. The method includes disposing a plurality of physical units, wherein each physical unit includes a physical block of each plane, and the physical blocks in the physical unit have a simultaneously-operable relationship. The method also includes writing data in a single plane access mode when a host system does not update all the physical blocks in an updated the physical unit. The method further includes writing the data in a multi-planes access mode when the host system updates all the physical blocks in the updated physical unit, wherein the physical blocks for writing the data have the simultaneously-operable relationship. | 02-18-2010 |
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| 20080197435 | Wafer level image sensor package with die receiving cavity and method of making the same - The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection. | 08-21-2008 |
| 20080211075 | IMAGE SENSOR CHIP SCALE PACKAGE HAVING INTER-ADHESION WITH GAP AND METHOD OF THE SAME - A structure of semiconductor device package having inter-adhesion with gap comprising: a chip with bonding pads and a sensor area embedded into a substrate with die window and inter-connecting through holes, wherein a RDL is formed over the substrate for coupling between the bonding pads and the inter-connecting through holes; a multiple rings (dam bar) formed over the substrate, the RDL, and the bonding pads area except the sensor area; an adhesive glues fill into the space of the multiple ring except the sensor area; and a transparency material bonded on the top of the multiple ring and the adhesive glues, wherein the adhesive glues adhesion between the transparency material and the multiple rings. | 09-04-2008 |
| 20080224248 | Image sensor module having build-in package cavity and the method of the same - The present invention provides an image sensor module having build-in package cavity and the Method of the same. An image sensor module structure comprising a substrate with a package receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate, and a package having a die with a micro lens disposed within the package receiving cavity. A dielectric layer is formed on the package and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder. | 09-18-2008 |
| 20080268647 | METHOD OF PLASMA ETCHING WITH PATTERN MASK - The present invention provides a method of plasma etching with pattern mask. There are two different devices in the two section of a wafer, comprising silicon and Gallium Arsenide (GaAs). The Silicon section is for general semiconductor. And the GaAs section is for RF device. The material of pad in the silicon is usually metal, and metal oxide is usually formed on the pads. The metal oxide is unwanted for further process; therefore it should be removed by plasma etching process. A film is attached to the surface of the substrate exposing the area need for etching. Then a mask is attached and aligned onto the film therefore exposing the area need for etching. Then plasma dry etching is applied on the substrate for removing the metal oxide. | 10-30-2008 |
| 20080274579 | Wafer level image sensor package with die receiving cavity and method of making the same - The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection. | 11-06-2008 |
| 20090008729 | IMAGE SENSOR PACKAGE UTILIZING A REMOVABLE PROTECTION FILM AND METHOD OF MAKING THE SAME - The present invention discloses a structure of image sensor package utilizing a removable protection film. The structure comprises a substrate with a die receiving cavity and inter-connecting through holes. Terminal pads are formed under the inter-connecting through holes and metal pads are formed on an upper surface of the substrate. A die is disposed within the die receiving cavity by an adhesion material. Bonding pads are formed on the upper edge of the die. Bonding wires are coupled to the metal pads and the bonding pads. A protection layer is formed on the micro lens area to protect the micro lens from particle contamination. A removable protection film is formed over the protection layer to protect the micro lens from water, oil, dust or temporary impact during the packaging and assembling process. | 01-08-2009 |
| 20090166873 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME - The interconnecting structure for a semiconductor die includes a die having bonding pads on an active surface; a core attached the side wall (edge) of the die by adhesion material; an isolating base adhered on the active surface of the die by adhesion glue; a through silicon via (TSV) open from the back side of the die to expose the bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via; solder balls melted on terminal pads, wherein the terminal pads located on the core and/or the die. | 07-02-2009 |
