Patent application number | Description | Published |
20080229134 | RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM - In processors having buffers to manage instruction flow referred to as a ReOrder Buffer (ROB) it is shown that these buffers are of the same approximate size of a checkpoint array for architected state. In a particular “morphing mode” in which a pair of processors can be configured to provide different functionalities on demand, a new “High-Reliability” (HR) mode is provided in which the ROB of one of the processors is used for a checkpoint array, and the pair of processors is made to run in lockstep on a single instruction stream under the control of the remaining ROB so as to provide redundant, hence highly-reliable computing. | 09-18-2008 |
20080229145 | Method and system for soft error recovery during processor execution - A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting code stage before the write-back stage that checks a value to be written by the processor for any error. The error-correcting code stage may correct any error in the value, and the pipeline may lack a recovery unit pipeline. | 09-18-2008 |
20080244186 | WRITE FILTER CACHE METHOD AND APPARATUS FOR PROTECTING THE MICROPROCESSOR CORE FROM SOFT ERRORS - A write filter cache system for protecting a microprocessor core from soft errors and method thereof are provided. In one aspect, data coming from a processor core to be written in primary cache memory, for instance, L1 cache memory system, is buffered in a write filter cache placed between the primary cache memory and the processor core. The data from the write filter is move to the main cache memory only if it is verified that main thread's data is soft error free, for instance, by comparing the main thread's data with that of its redundant thread. The main cache memory only keeps clean data associated with accepted checkpoints. | 10-02-2008 |
20080256383 | METHOD AND SYSTEM OF PREDICTING MICROPROCESSOR LIFETIME - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 10-16-2008 |
20080263326 | METHOD AND APPARATUS FOR AN EFFICIENT MULTI-PATH TRACE CACHE DESIGN - A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced. | 10-23-2008 |
20080270702 | METHOD AND APPARATUS FOR AN EFFICIENT MULTI-PATH TRACE CACHE DESIGN - A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced. | 10-30-2008 |
20080313509 | METHOD AND APPARATUS FOR PREVENTING SOFT ERROR ACCUMULATION IN REGISTER ARRAYS - A computer implemented method, apparatus, and computer usable program code for preventing soft error accumulation. A number of cycles between references to a register are counted. Instructions are injected that reference the register for preventing soft error accumulation in response to a determination that the number of cycles is greater than a threshold. | 12-18-2008 |
20090013207 | PREDICTING MICROPROCESSOR LIFETIME RELIABILITY USING ARCHITECTURE-LEVEL STRUCTURE-AWARE TECHNIQUES - A method of predicting the lifetime reliability of an integrated circuit device with respect to one or more failure mechanisms includes breaking down the integrated circuit device into structures; breaking down each structure into elements and devices; evaluating each device to determine whether the device is vulnerable to the failure mechanisms and eliminating devices determined not to be vulnerable; estimating, for each determined vulnerable device, the impact of a failure of the device on the functionality of the specific element associated therewith, and classifying the failure into a fatal failure or a non-fatal failure, wherein a fatal failure causes the element employing the given device to fail; determining, for those devices whose failures are fatal, an effective stress degree and/or time; determining one or more of a failure rate and a probability of fatal failure for the devices, and aggregating the same across the structures and the failure mechanisms. | 01-08-2009 |
20090048808 | METHOD AND APPARATUS FOR MONITORING AND ENHANCING ON-CHIP MICROPROCESSOR RELIABILITY - A system and method for projecting reliability to manage system functions includes an activity module which determines activity in the system. A reliability module interacts with the activity module to determine a reliability measurement for the module in real-time based upon the activity and measured operational quantities of the system. A management module manages actions of the system based upon the reliability measurement input from the reliability module. This may be to provide corrective action, to reallocate resources, increase reliability of the module, etc. | 02-19-2009 |
20090083492 | COST-CONSCIOUS PRE-EMPTIVE CACHE LINE DISPLACEMENT AND RELOCATION MECHANISMS - A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment. | 03-26-2009 |
20090144669 | METHOD AND ARRANGEMENT FOR ENHANCING PROCESS VARIABILITY AND LIFETIME RELIABILITY THROUGH 3D INTEGRATION - A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method. | 06-04-2009 |
20090144678 | METHOD AND ON-CHIP CONTROL APPARATUS FOR ENHANCING PROCESS RELIABILITY AND PROCESS VARIABILITY THROUGH 3D INTEGRATION - A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. | 06-04-2009 |
20100015732 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - Base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet, which provides the same functionality as one of the at least one non-functional chiplet is designed to provide, is vertically stacked. The at least one repair semiconductor chiplet provides the functionality that the at least one non-functional chiplet is designed to provide to the base semiconductor chip. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. In case a first attempt to repair the base semiconductor chip by stacking repair semiconductor chips is unsuccessful, additional repair semiconductor chips may be subsequently stacked to fully repair the base semiconductor chip. | 01-21-2010 |
20100083203 | Modeling System-Level Effects of Soft Errors - Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile. | 04-01-2010 |
20110286190 | Enhanced Modularity in Heterogeneous 3D Stacks - Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips. | 11-24-2011 |
20120144166 | CONTROL SIGNAL MEMOIZATION IN A MULTIPLE INSTRUCTION ISSUE MICROPROCESSOR - A dynamic predictive and/or exact caching mechanism is provided in various stages of a microprocessor pipeline so that various control signals can be stored and memorized in the course of program execution. Exact control signal vector caching may be done. Whenever an issue group is formed following instruction decode, register renaming, and dependency checking, an encoded copy of the issue group information can be cached under the tag of the leading instruction. The resulting dependency cache or control vector cache can be accessed right at the beginning of the instruction issue logic stage of the microprocessor pipeline the next time the corresponding group of instructions come up for re-execution. Since the encoded issue group bit pattern may be accessed in a single cycle out of the cache, the resulting microprocessor pipeline with this embodiment can be seen as two parallel pipes, where the shorter pipe is followed if there is a dependency cache or control vector cache hit. | 06-07-2012 |
20120268909 | Enhanced Modularity in Heterogeneous 3D Stacks - A three-dimensional computer processing chip stack that includes a host layer disposed on at least one other layer in the stack. The host layer includes cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other. The cavities are formed to accommodate the heterogeneous properties of the chips. The chips are joined to respective surfaces of the cavities, thereby forming an element having a smooth surface with respect to the host layer and the chips. | 10-25-2012 |
20120272040 | Enhanced Modularity in Heterogeneous 3D Stacks - A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack. | 10-25-2012 |
20120272202 | Enhanced Modularity in Heterogeneous 3D Stacks - A method for generating and implementing a three-dimensional ( | 10-25-2012 |
20130013977 | ADAPTIVE MULTI-BIT ERROR CORRECTION IN ENDURANCE LIMITED MEMORIES - Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device. | 01-10-2013 |
20140136553 | APPLIANCE FOR ACCELERATING GRAPH DATABASE MANAGEMENT AND ANALYTICS SYSTEMS - A query on a graph database can be efficiently performed employing a combination of an abstraction program and a graph analytics appliance. The abstraction program is generated from a query request employing an abstraction program compiler residing on a computational node, and includes programming instructions for performing parallel operations on graph data. The graph analytics appliance receives or generates the abstraction program, and runs the abstraction program on data fetched from a graph database to generate filtered data that is less than the fetched data. The filtered data is returned to the computational node. The bandwidth between the graph database and the graph analytic engine can be greater than the bandwidth between the computational node and the graph analytic engine in order to utilize processing capacity of the graph analytics appliance. | 05-15-2014 |
20140136555 | APPLIANCE FOR ACCELERATING GRAPH DATABASE MANAGEMENT AND ANALYTICS SYSTEMS - A query on a graph database can be efficiently performed employing a combination of an abstraction program and a graph analytics appliance. The abstraction program is generated from a query request employing an abstraction program compiler residing on a computational node, and includes programming instructions for performing parallel operations on graph data. The graph analytics appliance receives or generates the abstraction program, and runs the abstraction program on data fetched from a graph database to generate filtered data that is less than the fetched data. The filtered data is returned to the computational node. The bandwidth between the graph database and the graph analytic engine can be greater than the bandwidth between the computational node and the graph analytic engine in order to utilize processing capacity of the graph analytics appliance. | 05-15-2014 |
20140137129 | METHOD AND APPARATUS FOR EFFICIENT EXECUTION OF CONCURRENT PROCESSES ON A MULTITHREADED MESSAGE PASSING SYSTEM - A graph analytics appliance can be employed to extract data from a graph database in an efficient manner. The graph analytics appliance includes a router, a worklist scheduler, a processing unit, and an input/output unit. The router receives an abstraction program including a plurality of parallel algorithms for a query request from an abstraction program compiler residing on computational node or the graph analytics appliance. The worklist scheduler generates a prioritized plurality of parallel threads for executing the query request from the plurality of parallel algorithms. The processing unit executes multiple threads selected from the prioritized plurality of parallel threads. The input/output unit communicates with a graph database. | 05-15-2014 |
20140137130 | METHOD AND APPARATUS FOR EFFICIENT EXECUTION OF CONCURRENT PROCESSES ON A MULTITHREADED MESSAGE PASSING SYSTEM - A graph analytics appliance can be employed to extract data from a graph database in an efficient manner. The graph analytics appliance includes a router, a worklist scheduler, a processing unit, and an input/output unit. The router receives an abstraction program including a plurality of parallel algorithms for a query request from an abstraction program compiler residing on computational node or the graph analytics appliance. The worklist scheduler generates a prioritized plurality of parallel threads for executing the query request from the plurality of parallel algorithms. The processing unit executes multiple threads selected from the prioritized plurality of parallel threads. The input/output unit communicates with a graph database. | 05-15-2014 |
20140159803 | SEMICONDUCTOR CHIP REPAIR BY STACKING OF A BASE SEMICONDUCTOR CHIP AND A REPAIR SEMICONDUCTOR CHIP - In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional. | 06-12-2014 |