| Patent application number | Description | Published |
|---|
| 20090040314 | METHOD FOR RECORDING IMAGES IN ELECTRONIC DEVICE - A method for recording images in an electronic device is disclosed. The method includes the following steps. A scheduled time is set, and auto-login information is written into a registry of the electronic device. The electronic device enters a sleep state or a shutdown state. The state of the electronic device is switched to an operation state from the sleep state or the shutdown state, and the electronic device executes an auto-login according to the registry. Then, images are recorded at the scheduled time. | 02-12-2009 |
| 20090161014 | Method for Displaying TV Program on Computer - A method for displaying TV program on a computer system is described. An operation system of the computer system is started and a memory-resident program is simultaneously loaded to continuously detecting whether or not a predetermined TV signal transforming device is electrically coupled with the computer system and established. A TV displaying program is executed by means of the memory-resident program when the TV signal transforming device is electrically coupled with the computer system. | 06-25-2009 |
| 20090199240 | Computer System Capable of Instantly Showing Electronic Program Guide and Method for Using the Same - The invention relates to a method for showing an electronic program guide (EPG) on a computer screen. The computer has EPG data, a desktop application and a TV play program. The method includes the following steps. First, the desktop application program is launched, and an application window is displayed on the screen. Then, the EPG data is retrieved, and program information which is played is shown in the application window. Then, a message showing that the program information is clicked is received. Afterward, the TV play program is launched, and the TV program corresponding to program information is played. | 08-06-2009 |
| 20100185809 | Control System and Control Method of Virtual Memory - A control method of a virtual memory is adapted for using in a computer. The control method includes the following steps. First, a plurality of application programs executed in the computer are monitored. Second, the application programs are compared with at least a predetermined program, respectively. Third, the virtual memory of a solid state disk (SSD) is controlled to be turned on or turned off according to a comparing result. Herein, the virtual memory of the SSD is controlled to be turned on or turned off to enhance both lifetime of the SSD and operation efficiency of the computer. | 07-22-2010 |
| Patent application number | Description | Published |
|---|
| 20100098585 | Biosensor Package Structure with Micro-Fluidic Channel - A biosensor package structure with a micro-fluidic channel is provided. The biosensor package structure includes a substrate, a biochip, and a cover. The substrate has a first surface, a second surface, and an opening. The biochip is attached on the first surface. A bio-sensing area of the biochip is exposed to the opening of the substrate. The cover is attached on the second surface to cover the opening so as to form a micro-fluidic channel. By implementing the invention, the manufacturing process of the biosensor is simplified and the productivity is increased. | 04-22-2010 |
| 20100277203 | Edge-Missing Detector Structure - An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock. | 11-04-2010 |
| 20100315131 | Programmable Frequency Divider with Full Dividing Range - A programmable frequency divider with a full dividing range includes a plurality of cascaded 2/1 frequency dividers. Each of the 2/1 frequency dividers has a first input node, a first output node, a second input node, a second output node and a third input node. The first input node receives a first clock signal divided by the 2/1 frequency divider and outputted as a second clock signal through the first output node. A second logical signal is generated according to the second clock signal, the first clock signal and a first logical signal received from the second input node. The 2/1 frequency divider selectively switches to perform a divide-by-two or divide-by-one operation according to the second logical signal and a first divisor signal received from the third input nodes. The programmable frequency divider provides the full dividing range as the result of utilizing various divisor of the 2/1 frequency divider. | 12-16-2010 |
